CSRNG Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	7.000s	405.121us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	48.311us	5	5	100.00
V1	csr_rw	csrng_csr_rw	5.000s	131.495us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	22.000s	1.144ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	10.000s	325.012us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	260.894us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	131.495us	20	20	100.00
		csrng_csr_aliasing	10.000s	325.012us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	19.000s	1.556ms	200	200	100.00
V2	alerts	csrng_alert	1.133m	6.104ms	500	500	100.00
V2	err	csrng_err	31.000s	37.749us	499	500	99.80
V2	cmds	csrng_cmds	10.833m	67.908ms	50	50	100.00
V2	life cycle	csrng_cmds	10.833m	67.908ms	50	50	100.00
V2	stress_all	csrng_stress_all	40.633m	227.172ms	47	50	94.00
V2	intr_test	csrng_intr_test	4.000s	15.794us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	85.990us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	19.000s	1.277ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	19.000s	1.277ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	48.311us	5	5	100.00
		csrng_csr_rw	5.000s	131.495us	20	20	100.00
		csrng_csr_aliasing	10.000s	325.012us	5	5	100.00
		csrng_same_csr_outstanding	11.000s	914.324us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	48.311us	5	5	100.00
		csrng_csr_rw	5.000s	131.495us	20	20	100.00
		csrng_csr_aliasing	10.000s	325.012us	5	5	100.00
		csrng_same_csr_outstanding	11.000s	914.324us	20	20	100.00
V2		TOTAL			1436	1440	99.72
V2S	tl_intg_err	csrng_sec_cm	6.000s	72.644us	5	5	100.00
		csrng_tl_intg_err	12.000s	185.109us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	109.105us	50	50	100.00
		csrng_csr_rw	5.000s	131.495us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.133m	6.104ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	40.633m	227.172ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	19.000s	1.556ms	200	200	100.00
		csrng_err	31.000s	37.749us	499	500	99.80
		csrng_sec_cm	6.000s	72.644us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	19.000s	1.556ms	200	200	100.00
		csrng_err	31.000s	37.749us	499	500	99.80
		csrng_sec_cm	6.000s	72.644us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	19.000s	1.556ms	200	200	100.00
		csrng_err	31.000s	37.749us	499	500	99.80
		csrng_sec_cm	6.000s	72.644us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	19.000s	1.556ms	200	200	100.00
		csrng_err	31.000s	37.749us	499	500	99.80
		csrng_sec_cm	6.000s	72.644us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	19.000s	1.556ms	200	200	100.00
		csrng_err	31.000s	37.749us	499	500	99.80
		csrng_sec_cm	6.000s	72.644us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	19.000s	1.556ms	200	200	100.00
		csrng_err	31.000s	37.749us	499	500	99.80
		csrng_sec_cm	6.000s	72.644us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	19.000s	1.556ms	200	200	100.00
		csrng_err	31.000s	37.749us	499	500	99.80
		csrng_sec_cm	6.000s	72.644us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.133m	6.104ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	19.000s	1.556ms	200	200	100.00
		csrng_err	31.000s	37.749us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	40.633m	227.172ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.133m	6.104ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	12.000s	185.109us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	19.000s	1.556ms	200	200	100.00
		csrng_err	31.000s	37.749us	499	500	99.80
		csrng_sec_cm	6.000s	72.644us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	19.000s	1.556ms	200	200	100.00
		csrng_err	31.000s	37.749us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	19.000s	1.556ms	200	200	100.00
		csrng_err	31.000s	37.749us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	19.000s	1.556ms	200	200	100.00
		csrng_err	31.000s	37.749us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	19.000s	1.556ms	200	200	100.00
		csrng_err	31.000s	37.749us	499	500	99.80
		csrng_sec_cm	6.000s	72.644us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	19.000s	1.556ms	200	200	100.00
		csrng_err	31.000s	37.749us	499	500	99.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.283m	2.570ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1616	1630	99.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.32	98.37	96.16	99.09	96.76	91.84	100.00	97.14	90.34

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
  • Test csrng_stress_all_with_rand_reset has 10 failures.

    • 0.csrng_stress_all_with_rand_reset.69845705461340655311477933232365394007138213014362322499870659103935340010404
      Line 108, in log /workspaces/repo/scratch/os_regression_2024_08_22/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 806460023 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 806460023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.csrng_stress_all_with_rand_reset.11175892543107940083127478371134054458533866879224483876976358174471212037228
      Line 99, in log /workspaces/repo/scratch/os_regression_2024_08_22/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1583703997 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1583703997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
  • Test csrng_stress_all has 3 failures.

    • 25.csrng_stress_all.69029108245603199644212134176771005220728488841598994494863310884686298032769
      Line 168, in log /workspaces/repo/scratch/os_regression_2024_08_22/csrng-sim-xcelium/25.csrng_stress_all/latest/run.log

        UVM_ERROR @ 548860855 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 548860855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 36.csrng_stress_all.25092860894306383022675985249377199408671331952363619433422565401003163581955
      Line 161, in log /workspaces/repo/scratch/os_regression_2024_08_22/csrng-sim-xcelium/36.csrng_stress_all/latest/run.log

        UVM_ERROR @ 1453809016 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 1453809016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
  • Test csrng_err has 1 failures.

    • 99.csrng_err.94298961475674920189272041686940632617124030359687782453808756175530067410527
      Line 127, in log /workspaces/repo/scratch/os_regression_2024_08_22/csrng-sim-xcelium/99.csrng_err/latest/run.log

        UVM_ERROR @  14557670 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
        UVM_INFO @  14557670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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