CSRNG Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: `e733a8ef8a`

Branch: os_regression_2024_08_24

Simulator: XCELIUM

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	1.933m	22.840us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	2.233m	15.048us	5	5	100.00
V1	csr_rw	csrng_csr_rw	2.150m	48.825us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	2.900m	739.023us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	1.767m	71.145us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	2.150m	88.453us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	2.150m	48.825us	20	20	100.00
		csrng_csr_aliasing	1.767m	71.145us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	2.400m	281.127us	199	200	99.50
V2	alerts	csrng_alert	3.367m	363.115us	500	500	100.00
V2	err	csrng_err	3.083m	27.930us	499	500	99.80
V2	cmds	csrng_cmds	11.617m	23.946ms	50	50	100.00
V2	life cycle	csrng_cmds	11.617m	23.946ms	50	50	100.00
V2	stress_all	csrng_stress_all	27.117m	78.051ms	48	50	96.00
V2	intr_test	csrng_intr_test	1.950m	14.341us	50	50	100.00
V2	alert_test	csrng_alert_test	1.483m	25.843us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	2.483m	178.142us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	2.483m	178.142us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	2.233m	15.048us	5	5	100.00
		csrng_csr_rw	2.150m	48.825us	20	20	100.00
		csrng_csr_aliasing	1.767m	71.145us	5	5	100.00
		csrng_same_csr_outstanding	2.567m	24.531us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	2.233m	15.048us	5	5	100.00
		csrng_csr_rw	2.150m	48.825us	20	20	100.00
		csrng_csr_aliasing	1.767m	71.145us	5	5	100.00
		csrng_same_csr_outstanding	2.567m	24.531us	20	20	100.00
V2		TOTAL			1436	1440	99.72
V2S	tl_intg_err	csrng_sec_cm	18.000s	151.246us	5	5	100.00
		csrng_tl_intg_err	2.017m	132.871us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	1.483m	41.025us	50	50	100.00
		csrng_csr_rw	2.150m	48.825us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	3.367m	363.115us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	27.117m	78.051ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	2.400m	281.127us	199	200	99.50
		csrng_err	3.083m	27.930us	499	500	99.80
		csrng_sec_cm	18.000s	151.246us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	2.400m	281.127us	199	200	99.50
		csrng_err	3.083m	27.930us	499	500	99.80
		csrng_sec_cm	18.000s	151.246us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	2.400m	281.127us	199	200	99.50
		csrng_err	3.083m	27.930us	499	500	99.80
		csrng_sec_cm	18.000s	151.246us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	2.400m	281.127us	199	200	99.50
		csrng_err	3.083m	27.930us	499	500	99.80
		csrng_sec_cm	18.000s	151.246us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	2.400m	281.127us	199	200	99.50
		csrng_err	3.083m	27.930us	499	500	99.80
		csrng_sec_cm	18.000s	151.246us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	2.400m	281.127us	199	200	99.50
		csrng_err	3.083m	27.930us	499	500	99.80
		csrng_sec_cm	18.000s	151.246us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	2.400m	281.127us	199	200	99.50
		csrng_err	3.083m	27.930us	499	500	99.80
		csrng_sec_cm	18.000s	151.246us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	3.367m	363.115us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	2.400m	281.127us	199	200	99.50
		csrng_err	3.083m	27.930us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	27.117m	78.051ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	3.367m	363.115us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	2.017m	132.871us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	2.400m	281.127us	199	200	99.50
		csrng_err	3.083m	27.930us	499	500	99.80
		csrng_sec_cm	18.000s	151.246us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	2.400m	281.127us	199	200	99.50
		csrng_err	3.083m	27.930us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	2.400m	281.127us	199	200	99.50
		csrng_err	3.083m	27.930us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	2.400m	281.127us	199	200	99.50
		csrng_err	3.083m	27.930us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	2.400m	281.127us	199	200	99.50
		csrng_err	3.083m	27.930us	499	500	99.80
		csrng_sec_cm	18.000s	151.246us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	2.400m	281.127us	199	200	99.50
		csrng_err	3.083m	27.930us	499	500	99.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.283m	3.326ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1616	1630	99.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.33	98.37	96.16	99.09	96.76	91.84	100.00	97.14	90.65

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 7 failures:
- Test csrng_stress_all_with_rand_reset has 7 failures.
  - 0.csrng_stress_all_with_rand_reset.61917739479848981457892934809123642561815310529698928289011205462093027093468
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_08_24/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 117375823 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 117375823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.79965745111021189199801675689144464935460124034094293948081782807853167611744
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_08_24/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 164281160 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 164281160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 3 failures:

Test csrng_stress_all_with_rand_reset has 3 failures.

3.csrng_stress_all_with_rand_reset.102255095330584024921967223305110439320471271001755970593006941139955996672819
Line 115, in log /workspaces/repo/scratch/os_regression_2024_08_24/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  23650343 ps: uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer.m_edn_push_seq[0] already started
  UVM_INFO @  23650343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.csrng_stress_all_with_rand_reset.25525736962821276392053772541481344524936026738956951936598379751011347512089
Line 103, in log /workspaces/repo/scratch/os_regression_2024_08_24/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 108309774 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @ 108309774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 3.csrng_stress_all.23287469987729071090944580104322851711476212912993817911723900192629572169711
    Line 170, in log /workspaces/repo/scratch/os_regression_2024_08_24/csrng-sim-xcelium/3.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 281592027 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 281592027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 10.csrng_stress_all.69819279006599211032542197403728377817807633571884999008911710992641588177769
    Line 174, in log /workspaces/repo/scratch/os_regression_2024_08_24/csrng-sim-xcelium/10.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 8548908457 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 8548908457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:

Test csrng_intr has 1 failures.

173.csrng_intr.85508622820418136766739449826900731693247689490821113162352520071726768506180
Line 127, in log /workspaces/repo/scratch/os_regression_2024_08_24/csrng-sim-xcelium/173.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_24/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 68707529 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  68707529 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  68707529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 444.csrng_err.56651327772955939569476735358603519384879273320628114189647220521278497857998
    Line 127, in log /workspaces/repo/scratch/os_regression_2024_08_24/csrng-sim-xcelium/444.csrng_err/latest/run.log
```
  UVM_ERROR @   5312684 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @   5312684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```