CSRNG Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Simulator: XCELIUM

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	1.050m	17.917us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	1.550m	323.209us	5	5	100.00
V1	csr_rw	csrng_csr_rw	1.550m	75.593us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	1.550m	92.381us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	1.517m	29.825us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	1.733m	53.758us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	1.550m	75.593us	20	20	100.00
		csrng_csr_aliasing	1.517m	29.825us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	1.183m	289.386us	199	200	99.50
V2	alerts	csrng_alert	2.517m	1.181ms	500	500	100.00
V2	err	csrng_err	2.817m	21.274us	500	500	100.00
V2	cmds	csrng_cmds	9.383m	30.680ms	50	50	100.00
V2	life cycle	csrng_cmds	9.383m	30.680ms	50	50	100.00
V2	stress_all	csrng_stress_all	55.150m	261.445ms	49	50	98.00
V2	intr_test	csrng_intr_test	1.533m	149.732us	50	50	100.00
V2	alert_test	csrng_alert_test	49.000s	14.626us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	2.500m	97.204us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	2.500m	97.204us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	1.550m	323.209us	5	5	100.00
		csrng_csr_rw	1.550m	75.593us	20	20	100.00
		csrng_csr_aliasing	1.517m	29.825us	5	5	100.00
		csrng_same_csr_outstanding	1.683m	213.888us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	1.550m	323.209us	5	5	100.00
		csrng_csr_rw	1.550m	75.593us	20	20	100.00
		csrng_csr_aliasing	1.517m	29.825us	5	5	100.00
		csrng_same_csr_outstanding	1.683m	213.888us	20	20	100.00
V2		TOTAL			1438	1440	99.86
V2S	tl_intg_err	csrng_sec_cm	33.000s	123.477us	5	5	100.00
		csrng_tl_intg_err	1.900m	46.060us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	58.000s	19.574us	50	50	100.00
		csrng_csr_rw	1.550m	75.593us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	2.517m	1.181ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	55.150m	261.445ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	1.183m	289.386us	199	200	99.50
		csrng_err	2.817m	21.274us	500	500	100.00
		csrng_sec_cm	33.000s	123.477us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	1.183m	289.386us	199	200	99.50
		csrng_err	2.817m	21.274us	500	500	100.00
		csrng_sec_cm	33.000s	123.477us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	1.183m	289.386us	199	200	99.50
		csrng_err	2.817m	21.274us	500	500	100.00
		csrng_sec_cm	33.000s	123.477us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	1.183m	289.386us	199	200	99.50
		csrng_err	2.817m	21.274us	500	500	100.00
		csrng_sec_cm	33.000s	123.477us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	1.183m	289.386us	199	200	99.50
		csrng_err	2.817m	21.274us	500	500	100.00
		csrng_sec_cm	33.000s	123.477us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	1.183m	289.386us	199	200	99.50
		csrng_err	2.817m	21.274us	500	500	100.00
		csrng_sec_cm	33.000s	123.477us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	1.183m	289.386us	199	200	99.50
		csrng_err	2.817m	21.274us	500	500	100.00
		csrng_sec_cm	33.000s	123.477us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	2.517m	1.181ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	1.183m	289.386us	199	200	99.50
		csrng_err	2.817m	21.274us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	55.150m	261.445ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	2.517m	1.181ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	1.900m	46.060us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	1.183m	289.386us	199	200	99.50
		csrng_err	2.817m	21.274us	500	500	100.00
		csrng_sec_cm	33.000s	123.477us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	1.183m	289.386us	199	200	99.50
		csrng_err	2.817m	21.274us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	1.183m	289.386us	199	200	99.50
		csrng_err	2.817m	21.274us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	1.183m	289.386us	199	200	99.50
		csrng_err	2.817m	21.274us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	1.183m	289.386us	199	200	99.50
		csrng_err	2.817m	21.274us	500	500	100.00
		csrng_sec_cm	33.000s	123.477us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	1.183m	289.386us	199	200	99.50
		csrng_err	2.817m	21.274us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	4.233m	12.865ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1618	1630	99.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.24	98.32	96.06	99.02	96.70	91.77	100.00	96.78	90.34

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.46771983434202742835812302081063131516992026682731357925695394128105879153685
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_08_26/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 396701872 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 396701872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.60236341156159132691617579924622739444774277111871366092482873598888550703457
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_08_26/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 424984528 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 424984528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

3.csrng_stress_all_with_rand_reset.37259546857306654941486836189935571957546503079380320851472718301302202412849
Line 105, in log /workspaces/repo/scratch/os_regression_2024_08_26/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  20687608 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  20687608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.csrng_stress_all_with_rand_reset.172415065176687077070934277441092991985606954133305419850008577011166106843
Line 100, in log /workspaces/repo/scratch/os_regression_2024_08_26/csrng-sim-xcelium/7.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  30876003 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  30876003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 28.csrng_stress_all.97782657689430339424372594491966836566206862467922267241954343389082139008386
    Line 153, in log /workspaces/repo/scratch/os_regression_2024_08_26/csrng-sim-xcelium/28.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1643883288 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1643883288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:

Test csrng_intr has 1 failures.

97.csrng_intr.96187061399746492947282489352977959158860271363048323009719382265703081423353
Line 127, in log /workspaces/repo/scratch/os_regression_2024_08_26/csrng-sim-xcelium/97.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_26/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 43278215 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  43278215 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  43278215 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---