CSRNG Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Simulator: XCELIUM

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	7.000s	240.447us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	16.959us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	172.448us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	40.000s	1.078ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	150.058us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	6.000s	134.528us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	172.448us	20	20	100.00
		csrng_csr_aliasing	8.000s	150.058us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	29.000s	1.790ms	198	200	99.00
V2	alerts	csrng_alert	1.400m	5.061ms	500	500	100.00
V2	err	csrng_err	18.000s	76.732us	500	500	100.00
V2	cmds	csrng_cmds	10.317m	42.812ms	50	50	100.00
V2	life cycle	csrng_cmds	10.317m	42.812ms	50	50	100.00
V2	stress_all	csrng_stress_all	26.467m	60.926ms	47	50	94.00
V2	intr_test	csrng_intr_test	4.000s	37.749us	50	50	100.00
V2	alert_test	csrng_alert_test	7.000s	193.601us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	22.000s	1.525ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	22.000s	1.525ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	16.959us	5	5	100.00
		csrng_csr_rw	6.000s	172.448us	20	20	100.00
		csrng_csr_aliasing	8.000s	150.058us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	111.357us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	16.959us	5	5	100.00
		csrng_csr_rw	6.000s	172.448us	20	20	100.00
		csrng_csr_aliasing	8.000s	150.058us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	111.357us	20	20	100.00
V2		TOTAL			1435	1440	99.65
V2S	tl_intg_err	csrng_sec_cm	8.000s	89.320us	5	5	100.00
		csrng_tl_intg_err	1.917m	3.418ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	31.772us	50	50	100.00
		csrng_csr_rw	6.000s	172.448us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.400m	5.061ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	26.467m	60.926ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	29.000s	1.790ms	198	200	99.00
		csrng_err	18.000s	76.732us	500	500	100.00
		csrng_sec_cm	8.000s	89.320us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	29.000s	1.790ms	198	200	99.00
		csrng_err	18.000s	76.732us	500	500	100.00
		csrng_sec_cm	8.000s	89.320us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	29.000s	1.790ms	198	200	99.00
		csrng_err	18.000s	76.732us	500	500	100.00
		csrng_sec_cm	8.000s	89.320us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	29.000s	1.790ms	198	200	99.00
		csrng_err	18.000s	76.732us	500	500	100.00
		csrng_sec_cm	8.000s	89.320us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	29.000s	1.790ms	198	200	99.00
		csrng_err	18.000s	76.732us	500	500	100.00
		csrng_sec_cm	8.000s	89.320us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	29.000s	1.790ms	198	200	99.00
		csrng_err	18.000s	76.732us	500	500	100.00
		csrng_sec_cm	8.000s	89.320us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	29.000s	1.790ms	198	200	99.00
		csrng_err	18.000s	76.732us	500	500	100.00
		csrng_sec_cm	8.000s	89.320us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.400m	5.061ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	29.000s	1.790ms	198	200	99.00
		csrng_err	18.000s	76.732us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	26.467m	60.926ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.400m	5.061ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	1.917m	3.418ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	29.000s	1.790ms	198	200	99.00
		csrng_err	18.000s	76.732us	500	500	100.00
		csrng_sec_cm	8.000s	89.320us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	29.000s	1.790ms	198	200	99.00
		csrng_err	18.000s	76.732us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	29.000s	1.790ms	198	200	99.00
		csrng_err	18.000s	76.732us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	29.000s	1.790ms	198	200	99.00
		csrng_err	18.000s	76.732us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	29.000s	1.790ms	198	200	99.00
		csrng_err	18.000s	76.732us	500	500	100.00
		csrng_sec_cm	8.000s	89.320us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	29.000s	1.790ms	198	200	99.00
		csrng_err	18.000s	76.732us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.683m	8.656ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1615	1630	99.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.36	98.39	96.21	99.09	96.81	91.90	100.00	97.32	90.76

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.111379519310882681488436905658768588263396733265582164409991076354041923856503
    Line 118, in log /workspaces/repo/scratch/os_regression_2024_08_28/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2556531879 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2556531879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.20279148045909430612618290213263892030716209799799062810547110639014492851597
    Line 104, in log /workspaces/repo/scratch/os_regression_2024_08_28/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 8656416656 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 8656416656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 1.csrng_stress_all.29500718905515293795649412292974439236557130889033707796754153533754527768166
    Line 145, in log /workspaces/repo/scratch/os_regression_2024_08_28/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 3641059903 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 3641059903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.csrng_stress_all.26908064794591564330327085896330615927594952393010886423026372303546756820309
    Line 131, in log /workspaces/repo/scratch/os_regression_2024_08_28/csrng-sim-xcelium/29.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  35890638 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  35890638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

1.csrng_stress_all_with_rand_reset.8433283170849651798487965899819166399458045554065488211533167867248064072369
Line 103, in log /workspaces/repo/scratch/os_regression_2024_08_28/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  17952873 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  17952873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.csrng_stress_all_with_rand_reset.24711541209598655593259699237106672122782368245864454482802310548491328513522
Line 106, in log /workspaces/repo/scratch/os_regression_2024_08_28/csrng-sim-xcelium/9.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @   9657067 ps: uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer.m_edn_push_seq[0] already started
  UVM_INFO @   9657067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 2 failures:

Test csrng_intr has 2 failures.

14.csrng_intr.10044188051618453824463041058834525254065498041606601602496529054541782688857
Line 127, in log /workspaces/repo/scratch/os_regression_2024_08_28/csrng-sim-xcelium/14.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 328269071 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 328269071 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 328269071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

103.csrng_intr.6547031915274566225579716672635359092414991983718178166144324780091477341053
Line 127, in log /workspaces/repo/scratch/os_regression_2024_08_28/csrng-sim-xcelium/103.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 73792848 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  73792848 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  73792848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---