CSRNG Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Simulator: XCELIUM

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	438.816us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	1.050m	14.002us	5	5	100.00
V1	csr_rw	csrng_csr_rw	1.850m	68.048us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	1.533m	1.789ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	1.150m	33.219us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	2.150m	13.861us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	1.850m	68.048us	20	20	100.00
		csrng_csr_aliasing	1.150m	33.219us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	1.883m	90.862us	199	200	99.50
V2	alerts	csrng_alert	2.450m	3.393ms	500	500	100.00
V2	err	csrng_err	2.400m	20.392us	499	500	99.80
V2	cmds	csrng_cmds	9.433m	47.348ms	50	50	100.00
V2	life cycle	csrng_cmds	9.433m	47.348ms	50	50	100.00
V2	stress_all	csrng_stress_all	39.200m	118.475ms	47	50	94.00
V2	intr_test	csrng_intr_test	1.800m	12.392us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	140.856us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	2.083m	404.346us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	2.083m	404.346us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	1.050m	14.002us	5	5	100.00
		csrng_csr_rw	1.850m	68.048us	20	20	100.00
		csrng_csr_aliasing	1.150m	33.219us	5	5	100.00
		csrng_same_csr_outstanding	2.200m	187.099us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	1.050m	14.002us	5	5	100.00
		csrng_csr_rw	1.850m	68.048us	20	20	100.00
		csrng_csr_aliasing	1.150m	33.219us	5	5	100.00
		csrng_same_csr_outstanding	2.200m	187.099us	20	20	100.00
V2		TOTAL			1435	1440	99.65
V2S	tl_intg_err	csrng_sec_cm	9.000s	440.164us	5	5	100.00
		csrng_tl_intg_err	1.967m	613.749us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	106.833us	50	50	100.00
		csrng_csr_rw	1.850m	68.048us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	2.450m	3.393ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	39.200m	118.475ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	1.883m	90.862us	199	200	99.50
		csrng_err	2.400m	20.392us	499	500	99.80
		csrng_sec_cm	9.000s	440.164us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	1.883m	90.862us	199	200	99.50
		csrng_err	2.400m	20.392us	499	500	99.80
		csrng_sec_cm	9.000s	440.164us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	1.883m	90.862us	199	200	99.50
		csrng_err	2.400m	20.392us	499	500	99.80
		csrng_sec_cm	9.000s	440.164us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	1.883m	90.862us	199	200	99.50
		csrng_err	2.400m	20.392us	499	500	99.80
		csrng_sec_cm	9.000s	440.164us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	1.883m	90.862us	199	200	99.50
		csrng_err	2.400m	20.392us	499	500	99.80
		csrng_sec_cm	9.000s	440.164us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	1.883m	90.862us	199	200	99.50
		csrng_err	2.400m	20.392us	499	500	99.80
		csrng_sec_cm	9.000s	440.164us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	1.883m	90.862us	199	200	99.50
		csrng_err	2.400m	20.392us	499	500	99.80
		csrng_sec_cm	9.000s	440.164us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	2.450m	3.393ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	1.883m	90.862us	199	200	99.50
		csrng_err	2.400m	20.392us	499	500	99.80
V2S	sec_cm_constants_lc_gated	csrng_stress_all	39.200m	118.475ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	2.450m	3.393ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	1.967m	613.749us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	1.883m	90.862us	199	200	99.50
		csrng_err	2.400m	20.392us	499	500	99.80
		csrng_sec_cm	9.000s	440.164us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	1.883m	90.862us	199	200	99.50
		csrng_err	2.400m	20.392us	499	500	99.80
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	1.883m	90.862us	199	200	99.50
		csrng_err	2.400m	20.392us	499	500	99.80
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	1.883m	90.862us	199	200	99.50
		csrng_err	2.400m	20.392us	499	500	99.80
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	1.883m	90.862us	199	200	99.50
		csrng_err	2.400m	20.392us	499	500	99.80
		csrng_sec_cm	9.000s	440.164us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	1.883m	90.862us	199	200	99.50
		csrng_err	2.400m	20.392us	499	500	99.80
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.367m	2.435ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1615	1630	99.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	6	66.67
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.37	98.39	96.21	99.12	96.76	91.90	100.00	97.32	90.76

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test csrng_stress_all_with_rand_reset has 9 failures.
  - 0.csrng_stress_all_with_rand_reset.73628324771425605450754752302196629427679459879491279903852217064256355950874
    Line 118, in log /workspaces/repo/scratch/os_regression_2024_08_31/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 383743973 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 383743973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.csrng_stress_all_with_rand_reset.83062294989064862674310033111933521074624075162432230980835997315329318822232
    Line 105, in log /workspaces/repo/scratch/os_regression_2024_08_31/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2435369247 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2435369247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 29.csrng_stress_all.59677913977505647475170754173252306104541228480647730010177683084465147214808
    Line 138, in log /workspaces/repo/scratch/os_regression_2024_08_31/csrng-sim-xcelium/29.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 1608226231 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 1608226231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.csrng_stress_all.38081265818547121471802579559065622724139842568398048801859613357174381215138
    Line 142, in log /workspaces/repo/scratch/os_regression_2024_08_31/csrng-sim-xcelium/40.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 555002417 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 555002417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 4.csrng_stress_all_with_rand_reset.15272205650283081972730075851560515730369155531700601785593883251746914448298
    Line 101, in log /workspaces/repo/scratch/os_regression_2024_08_31/csrng-sim-xcelium/4.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  94634560 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  94634560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 1 failures:
- Test csrng_err has 1 failures.
  - 149.csrng_err.22511714621614732709380966282065037692473459447039559879634646950945801503117
    Line 127, in log /workspaces/repo/scratch/os_regression_2024_08_31/csrng-sim-xcelium/149.csrng_err/latest/run.log
```
  UVM_ERROR @  42696966 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  42696966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:

Test csrng_intr has 1 failures.

197.csrng_intr.75731782523496510172128107259744686437305862873564863973030879486451935191661
Line 127, in log /workspaces/repo/scratch/os_regression_2024_08_31/csrng-sim-xcelium/197.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_31/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 117111690 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 117111690 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 117111690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---