CSRNG Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: `29d22a60a2`

Branch: os_regression_2024_10_08

Simulator: XCELIUM

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	1.350m	67.771us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	106.345us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	51.971us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	52.000s	1.888ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	22.000s	874.586us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	275.867us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	51.971us	20	20	100.00
		csrng_csr_aliasing	22.000s	874.586us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	1.517m	558.356us	198	200	99.00
V2	alerts	csrng_alert	1.783m	565.848us	500	500	100.00
V2	err	csrng_err	2.050m	44.118us	500	500	100.00
V2	cmds	csrng_cmds	8.583m	33.632ms	50	50	100.00
V2	life cycle	csrng_cmds	8.583m	33.632ms	50	50	100.00
V2	stress_all	csrng_stress_all	31.383m	98.219ms	48	50	96.00
V2	intr_test	csrng_intr_test	5.000s	114.967us	50	50	100.00
V2	alert_test	csrng_alert_test	1.317m	24.348us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	25.000s	1.246ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	25.000s	1.246ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	106.345us	5	5	100.00
		csrng_csr_rw	6.000s	51.971us	20	20	100.00
		csrng_csr_aliasing	22.000s	874.586us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	386.804us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	106.345us	5	5	100.00
		csrng_csr_rw	6.000s	51.971us	20	20	100.00
		csrng_csr_aliasing	22.000s	874.586us	5	5	100.00
		csrng_same_csr_outstanding	9.000s	386.804us	20	20	100.00
V2		TOTAL			1436	1440	99.72
V2S	tl_intg_err	csrng_sec_cm	53.000s	71.097us	5	5	100.00
		csrng_tl_intg_err	22.000s	1.230ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	1.367m	13.214us	50	50	100.00
		csrng_csr_rw	6.000s	51.971us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.783m	565.848us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	31.383m	98.219ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	1.517m	558.356us	198	200	99.00
		csrng_err	2.050m	44.118us	500	500	100.00
		csrng_sec_cm	53.000s	71.097us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	1.517m	558.356us	198	200	99.00
		csrng_err	2.050m	44.118us	500	500	100.00
		csrng_sec_cm	53.000s	71.097us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	1.517m	558.356us	198	200	99.00
		csrng_err	2.050m	44.118us	500	500	100.00
		csrng_sec_cm	53.000s	71.097us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	1.517m	558.356us	198	200	99.00
		csrng_err	2.050m	44.118us	500	500	100.00
		csrng_sec_cm	53.000s	71.097us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	1.517m	558.356us	198	200	99.00
		csrng_err	2.050m	44.118us	500	500	100.00
		csrng_sec_cm	53.000s	71.097us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	1.517m	558.356us	198	200	99.00
		csrng_err	2.050m	44.118us	500	500	100.00
		csrng_sec_cm	53.000s	71.097us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	1.517m	558.356us	198	200	99.00
		csrng_err	2.050m	44.118us	500	500	100.00
		csrng_sec_cm	53.000s	71.097us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.783m	565.848us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	1.517m	558.356us	198	200	99.00
		csrng_err	2.050m	44.118us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	31.383m	98.219ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.783m	565.848us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	22.000s	1.230ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	1.517m	558.356us	198	200	99.00
		csrng_err	2.050m	44.118us	500	500	100.00
		csrng_sec_cm	53.000s	71.097us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	1.517m	558.356us	198	200	99.00
		csrng_err	2.050m	44.118us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	1.517m	558.356us	198	200	99.00
		csrng_err	2.050m	44.118us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	1.517m	558.356us	198	200	99.00
		csrng_err	2.050m	44.118us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	1.517m	558.356us	198	200	99.00
		csrng_err	2.050m	44.118us	500	500	100.00
		csrng_sec_cm	53.000s	71.097us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	1.517m	558.356us	198	200	99.00
		csrng_err	2.050m	44.118us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	3.250m	4.500ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1616	1630	99.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.39	98.41	96.27	99.14	96.81	91.90	100.00	97.41	90.65

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
- Test csrng_stress_all_with_rand_reset has 9 failures.
  - 0.csrng_stress_all_with_rand_reset.76346894469032688245796124932440418996698188250002256059449803516259360703708
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_10_08/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 106333548 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 106333548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.16711115034070972486219542006601571899451235100911360001305340208874154739022
    Line 116, in log /workspaces/repo/scratch/os_regression_2024_10_08/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3862268091 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3862268091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
- Test csrng_stress_all has 2 failures.
  - 0.csrng_stress_all.86918204060596668141656775356298316136589369530028309593902171420599142263030
    Line 140, in log /workspaces/repo/scratch/os_regression_2024_10_08/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log
```
  UVM_ERROR @  71681340 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @  71681340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.csrng_stress_all.114100905284138919127007619680389982564614111735722226501993564317780966194627
    Line 146, in log /workspaces/repo/scratch/os_regression_2024_10_08/csrng-sim-xcelium/14.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 5072124244 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 5072124244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 2 failures:

Test csrng_intr has 2 failures.

82.csrng_intr.48288762088581438864970978862573748881902638767132802355347097332896477017560
Line 127, in log /workspaces/repo/scratch/os_regression_2024_10_08/csrng-sim-xcelium/82.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 147467805 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 147467805 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 147467805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

175.csrng_intr.18320116643002228003226480325332948920607032190053969585424059486358311984056
Line 127, in log /workspaces/repo/scratch/os_regression_2024_10_08/csrng-sim-xcelium/175.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_08/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 367392793 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 367392793 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 367392793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
- Test csrng_stress_all_with_rand_reset has 1 failures.
  - 1.csrng_stress_all_with_rand_reset.14614940082786245910136124079788354883847859794693141263348378018958530739231
    Line 100, in log /workspaces/repo/scratch/os_regression_2024_10_08/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  26879539 ps: uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer.m_edn_push_seq[0] already started
  UVM_INFO @  26879539 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```