CSRNG Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	8.000s	176.905us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	23.495us	5	5	100.00
V1	csr_rw	csrng_csr_rw	8.000s	15.821us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	49.000s	1.517ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	9.000s	80.853us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	12.000s	22.756us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	8.000s	15.821us	20	20	100.00
		csrng_csr_aliasing	9.000s	80.853us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	33.000s	1.863ms	200	200	100.00
V2	alerts	csrng_alert	1.600m	6.922ms	500	500	100.00
V2	err	csrng_err	6.000s	31.773us	500	500	100.00
V2	cmds	csrng_cmds	14.200m	45.034ms	50	50	100.00
V2	life cycle	csrng_cmds	14.200m	45.034ms	50	50	100.00
V2	stress_all	csrng_stress_all	37.100m	46.282ms	48	50	96.00
V2	intr_test	csrng_intr_test	24.000s	20.932us	50	50	100.00
V2	alert_test	csrng_alert_test	6.000s	134.380us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	24.000s	1.476ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	24.000s	1.476ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	23.495us	5	5	100.00
		csrng_csr_rw	8.000s	15.821us	20	20	100.00
		csrng_csr_aliasing	9.000s	80.853us	5	5	100.00
		csrng_same_csr_outstanding	12.000s	76.119us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	23.495us	5	5	100.00
		csrng_csr_rw	8.000s	15.821us	20	20	100.00
		csrng_csr_aliasing	9.000s	80.853us	5	5	100.00
		csrng_same_csr_outstanding	12.000s	76.119us	20	20	100.00
V2		TOTAL			1438	1440	99.86
V2S	tl_intg_err	csrng_sec_cm	12.000s	155.302us	5	5	100.00
		csrng_tl_intg_err	24.000s	141.570us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	112.767us	50	50	100.00
		csrng_csr_rw	8.000s	15.821us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.600m	6.922ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	37.100m	46.282ms	48	50	96.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	33.000s	1.863ms	200	200	100.00
		csrng_err	6.000s	31.773us	500	500	100.00
		csrng_sec_cm	12.000s	155.302us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	33.000s	1.863ms	200	200	100.00
		csrng_err	6.000s	31.773us	500	500	100.00
		csrng_sec_cm	12.000s	155.302us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	33.000s	1.863ms	200	200	100.00
		csrng_err	6.000s	31.773us	500	500	100.00
		csrng_sec_cm	12.000s	155.302us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	33.000s	1.863ms	200	200	100.00
		csrng_err	6.000s	31.773us	500	500	100.00
		csrng_sec_cm	12.000s	155.302us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	33.000s	1.863ms	200	200	100.00
		csrng_err	6.000s	31.773us	500	500	100.00
		csrng_sec_cm	12.000s	155.302us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	33.000s	1.863ms	200	200	100.00
		csrng_err	6.000s	31.773us	500	500	100.00
		csrng_sec_cm	12.000s	155.302us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	33.000s	1.863ms	200	200	100.00
		csrng_err	6.000s	31.773us	500	500	100.00
		csrng_sec_cm	12.000s	155.302us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.600m	6.922ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	33.000s	1.863ms	200	200	100.00
		csrng_err	6.000s	31.773us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	37.100m	46.282ms	48	50	96.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.600m	6.922ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	24.000s	141.570us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	33.000s	1.863ms	200	200	100.00
		csrng_err	6.000s	31.773us	500	500	100.00
		csrng_sec_cm	12.000s	155.302us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	33.000s	1.863ms	200	200	100.00
		csrng_err	6.000s	31.773us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	33.000s	1.863ms	200	200	100.00
		csrng_err	6.000s	31.773us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	33.000s	1.863ms	200	200	100.00
		csrng_err	6.000s	31.773us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	33.000s	1.863ms	200	200	100.00
		csrng_err	6.000s	31.773us	500	500	100.00
		csrng_sec_cm	12.000s	155.302us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	33.000s	1.863ms	200	200	100.00
		csrng_err	6.000s	31.773us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.217m	5.011ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1618	1630	99.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	8	88.89
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.31	98.35	96.11	99.04	96.70	91.90	100.00	97.41	90.76

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
  • Test csrng_stress_all_with_rand_reset has 10 failures.

    • 0.csrng_stress_all_with_rand_reset.73980887791122132277844729384353465382490577989866324508810092422272566099871
      Line 103, in log /workspaces/repo/scratch/os_regression_2024_09_17/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1201786331 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1201786331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.csrng_stress_all_with_rand_reset.29317632210755998045985692655913513677899980150263230766012291579351638293644
      Line 97, in log /workspaces/repo/scratch/os_regression_2024_09_17/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 369515143 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 369515143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 8 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 2 failures:
  • Test csrng_stress_all has 2 failures.

    • 1.csrng_stress_all.31641355708922190912918906285464076437909895199151315490227481114486806666737
      Line 138, in log /workspaces/repo/scratch/os_regression_2024_09_17/csrng-sim-xcelium/1.csrng_stress_all/latest/run.log

        UVM_ERROR @ 6278689315 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 6278689315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 43.csrng_stress_all.88940632554716554762064257176595696105486952166862715895462668909556908307340
      Line 131, in log /workspaces/repo/scratch/os_regression_2024_09_17/csrng-sim-xcelium/43.csrng_stress_all/latest/run.log

        UVM_ERROR @  20511223 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  20511223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.09.12_10.14.43
• 2024.09.10_08.09.39
• 2024.09.05_04.19.11
• 2024.09.02_11.28.59
• 2024.08.29_23.10.58
• 2024.08.28_06.54.35