CSRNG Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: `8a1401d614`

Branch: os_regression_2024_10_11

Simulator: XCELIUM

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	1.233m	53.757us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	1.867m	46.486us	5	5	100.00
V1	csr_rw	csrng_csr_rw	1.217m	23.723us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	1.983m	549.603us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	1.700m	49.806us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	1.983m	31.935us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	1.217m	23.723us	20	20	100.00
		csrng_csr_aliasing	1.700m	49.806us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	1.133m	295.656us	199	200	99.50
V2	alerts	csrng_alert	2.450m	392.376us	500	500	100.00
V2	err	csrng_err	2.267m	41.908us	500	500	100.00
V2	cmds	csrng_cmds	9.550m	13.647ms	50	50	100.00
V2	life cycle	csrng_cmds	9.550m	13.647ms	50	50	100.00
V2	stress_all	csrng_stress_all	17.250m	69.373ms	47	50	94.00
V2	intr_test	csrng_intr_test	1.917m	17.561us	50	50	100.00
V2	alert_test	csrng_alert_test	1.233m	19.621us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	1.767m	745.032us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	1.767m	745.032us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	1.867m	46.486us	5	5	100.00
		csrng_csr_rw	1.217m	23.723us	20	20	100.00
		csrng_csr_aliasing	1.700m	49.806us	5	5	100.00
		csrng_same_csr_outstanding	2.033m	21.444us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	1.867m	46.486us	5	5	100.00
		csrng_csr_rw	1.217m	23.723us	20	20	100.00
		csrng_csr_aliasing	1.700m	49.806us	5	5	100.00
		csrng_same_csr_outstanding	2.033m	21.444us	20	20	100.00
V2		TOTAL			1436	1440	99.72
V2S	tl_intg_err	csrng_sec_cm	1.000m	291.859us	5	5	100.00
		csrng_tl_intg_err	1.917m	212.984us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	52.000s	14.583us	50	50	100.00
		csrng_csr_rw	1.217m	23.723us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	2.450m	392.376us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	17.250m	69.373ms	47	50	94.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	1.133m	295.656us	199	200	99.50
		csrng_err	2.267m	41.908us	500	500	100.00
		csrng_sec_cm	1.000m	291.859us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	1.133m	295.656us	199	200	99.50
		csrng_err	2.267m	41.908us	500	500	100.00
		csrng_sec_cm	1.000m	291.859us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	1.133m	295.656us	199	200	99.50
		csrng_err	2.267m	41.908us	500	500	100.00
		csrng_sec_cm	1.000m	291.859us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	1.133m	295.656us	199	200	99.50
		csrng_err	2.267m	41.908us	500	500	100.00
		csrng_sec_cm	1.000m	291.859us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	1.133m	295.656us	199	200	99.50
		csrng_err	2.267m	41.908us	500	500	100.00
		csrng_sec_cm	1.000m	291.859us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	1.133m	295.656us	199	200	99.50
		csrng_err	2.267m	41.908us	500	500	100.00
		csrng_sec_cm	1.000m	291.859us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	1.133m	295.656us	199	200	99.50
		csrng_err	2.267m	41.908us	500	500	100.00
		csrng_sec_cm	1.000m	291.859us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	2.450m	392.376us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	1.133m	295.656us	199	200	99.50
		csrng_err	2.267m	41.908us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	17.250m	69.373ms	47	50	94.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	2.450m	392.376us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	1.917m	212.984us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	1.133m	295.656us	199	200	99.50
		csrng_err	2.267m	41.908us	500	500	100.00
		csrng_sec_cm	1.000m	291.859us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	1.133m	295.656us	199	200	99.50
		csrng_err	2.267m	41.908us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	1.133m	295.656us	199	200	99.50
		csrng_err	2.267m	41.908us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	1.133m	295.656us	199	200	99.50
		csrng_err	2.267m	41.908us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	1.133m	295.656us	199	200	99.50
		csrng_err	2.267m	41.908us	500	500	100.00
		csrng_sec_cm	1.000m	291.859us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	1.133m	295.656us	199	200	99.50
		csrng_err	2.267m	41.908us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	2.683m	2.531ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1616	1630	99.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	7	77.78
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.37	98.39	96.21	99.12	96.81	91.84	100.00	97.41	90.76

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 8 failures:
- Test csrng_stress_all_with_rand_reset has 8 failures.
  - 0.csrng_stress_all_with_rand_reset.95897949181304683578756823870609871647091289030029065406598823053815360004745
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_10_11/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 101057324 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 101057324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.csrng_stress_all_with_rand_reset.5968758481920691026169246528175536712549757206080384734101494466796591247186
    Line 102, in log /workspaces/repo/scratch/os_regression_2024_10_11/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 994229893 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 994229893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 3 failures:
- Test csrng_stress_all has 3 failures.
  - 10.csrng_stress_all.80998078055929119867213549844596682392231532773538182265347949762293596681214
    Line 156, in log /workspaces/repo/scratch/os_regression_2024_10_11/csrng-sim-xcelium/10.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 9769584726 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 9769584726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.csrng_stress_all.51185978608772092360854959645599379924168687221691824919034750656612892957472
    Line 161, in log /workspaces/repo/scratch/os_regression_2024_10_11/csrng-sim-xcelium/37.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 361329646 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 361329646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 2 failures:

Test csrng_stress_all_with_rand_reset has 2 failures.

1.csrng_stress_all_with_rand_reset.114911488610569771315976651982637042391465440466336008263720913561056841860881
Line 103, in log /workspaces/repo/scratch/os_regression_2024_10_11/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @   7118906 ps: uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[0].m_cmd_push_agent.sequencer.m_edn_push_seq[0] already started
  UVM_INFO @   7118906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.csrng_stress_all_with_rand_reset.8947910381000012771666152218649888893420406697005687762849594775690576091803
Line 100, in log /workspaces/repo/scratch/os_regression_2024_10_11/csrng-sim-xcelium/3.csrng_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  31743437 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
  UVM_INFO @  31743437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 1 failures:

Test csrng_intr has 1 failures.

34.csrng_intr.34791732593832696737668409663104726556036862900689023196961138315349721348226
Line 127, in log /workspaces/repo/scratch/os_regression_2024_10_11/csrng-sim-xcelium/34.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_11/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 82477928 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  82477928 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  82477928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---