CSRNG Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: 78ad89d1aa

Branch: os_regression_2024_09_23

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	192.230us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	6.000s	23.333us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	38.282us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	1.433m	5.806ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	11.000s	477.014us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	9.000s	474.774us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	38.282us	20	20	100.00
		csrng_csr_aliasing	11.000s	477.014us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	50.000s	198.612us	200	200	100.00
V2	alerts	csrng_alert	2.033m	119.933us	500	500	100.00
V2	err	csrng_err	1.833m	53.673us	500	500	100.00
V2	cmds	csrng_cmds	11.400m	22.842ms	50	50	100.00
V2	life cycle	csrng_cmds	11.400m	22.842ms	50	50	100.00
V2	stress_all	csrng_stress_all	20.167m	44.631ms	45	50	90.00
V2	intr_test	csrng_intr_test	7.000s	159.977us	50	50	100.00
V2	alert_test	csrng_alert_test	7.000s	59.853us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	29.000s	1.588ms	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	29.000s	1.588ms	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	6.000s	23.333us	5	5	100.00
		csrng_csr_rw	6.000s	38.282us	20	20	100.00
		csrng_csr_aliasing	11.000s	477.014us	5	5	100.00
		csrng_same_csr_outstanding	17.000s	766.509us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	6.000s	23.333us	5	5	100.00
		csrng_csr_rw	6.000s	38.282us	20	20	100.00
		csrng_csr_aliasing	11.000s	477.014us	5	5	100.00
		csrng_same_csr_outstanding	17.000s	766.509us	20	20	100.00
V2		TOTAL			1435	1440	99.65
V2S	tl_intg_err	csrng_sec_cm	22.000s	933.774us	5	5	100.00
		csrng_tl_intg_err	15.000s	1.230ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	15.373us	50	50	100.00
		csrng_csr_rw	6.000s	38.282us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	2.033m	119.933us	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	20.167m	44.631ms	45	50	90.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	50.000s	198.612us	200	200	100.00
		csrng_err	1.833m	53.673us	500	500	100.00
		csrng_sec_cm	22.000s	933.774us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	50.000s	198.612us	200	200	100.00
		csrng_err	1.833m	53.673us	500	500	100.00
		csrng_sec_cm	22.000s	933.774us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	50.000s	198.612us	200	200	100.00
		csrng_err	1.833m	53.673us	500	500	100.00
		csrng_sec_cm	22.000s	933.774us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	50.000s	198.612us	200	200	100.00
		csrng_err	1.833m	53.673us	500	500	100.00
		csrng_sec_cm	22.000s	933.774us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	50.000s	198.612us	200	200	100.00
		csrng_err	1.833m	53.673us	500	500	100.00
		csrng_sec_cm	22.000s	933.774us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	50.000s	198.612us	200	200	100.00
		csrng_err	1.833m	53.673us	500	500	100.00
		csrng_sec_cm	22.000s	933.774us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	50.000s	198.612us	200	200	100.00
		csrng_err	1.833m	53.673us	500	500	100.00
		csrng_sec_cm	22.000s	933.774us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	2.033m	119.933us	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	50.000s	198.612us	200	200	100.00
		csrng_err	1.833m	53.673us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	20.167m	44.631ms	45	50	90.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	2.033m	119.933us	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	15.000s	1.230ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	50.000s	198.612us	200	200	100.00
		csrng_err	1.833m	53.673us	500	500	100.00
		csrng_sec_cm	22.000s	933.774us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	50.000s	198.612us	200	200	100.00
		csrng_err	1.833m	53.673us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	50.000s	198.612us	200	200	100.00
		csrng_err	1.833m	53.673us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	50.000s	198.612us	200	200	100.00
		csrng_err	1.833m	53.673us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	50.000s	198.612us	200	200	100.00
		csrng_err	1.833m	53.673us	500	500	100.00
		csrng_sec_cm	22.000s	933.774us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	50.000s	198.612us	200	200	100.00
		csrng_err	1.833m	53.673us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.467m	3.374ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1615	1630	99.08

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	8	88.89
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.26	98.32	96.06	99.02	96.65	91.84	100.00	96.89	90.65

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
  • Test csrng_stress_all_with_rand_reset has 9 failures.

    • 0.csrng_stress_all_with_rand_reset.74865423521290337439007163604263890787574007003607106265951723746273588654054
      Line 97, in log /workspaces/repo/scratch/os_regression_2024_09_23/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 494497716 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 494497716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.csrng_stress_all_with_rand_reset.11607614431072568206471674720641245545002567578246531205385141571614754391780
      Line 97, in log /workspaces/repo/scratch/os_regression_2024_09_23/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 235259312 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 235259312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 7 more failures.

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 5 failures:
  • Test csrng_stress_all has 5 failures.

    • 2.csrng_stress_all.6732167405302628843747711852323643975401388095361031063199448894307050178475
      Line 145, in log /workspaces/repo/scratch/os_regression_2024_09_23/csrng-sim-xcelium/2.csrng_stress_all/latest/run.log

        UVM_ERROR @ 3296633069 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @ 3296633069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 14.csrng_stress_all.87614808792560422323236333937399868728868285290357313161944155439288355051857
      Line 134, in log /workspaces/repo/scratch/os_regression_2024_09_23/csrng-sim-xcelium/14.csrng_stress_all/latest/run.log

        UVM_ERROR @  44049464 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  44049464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 3 more failures.

• UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 6.csrng_stress_all_with_rand_reset.90771693439514177697686907686050511810213723478799811477541182027003938865162
      Line 112, in log /workspaces/repo/scratch/os_regression_2024_09_23/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @   6844727 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
        UVM_INFO @   6844727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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