CSRNG Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: 1cb1c3d135

Branch: os_regression_2024_10_02

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	10.000s	258.651us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	7.000s	112.311us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	117.833us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	45.000s	1.038ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	12.000s	330.019us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	282.418us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	117.833us	20	20	100.00
		csrng_csr_aliasing	12.000s	330.019us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	42.000s	1.755ms	200	200	100.00
V2	alerts	csrng_alert	1.883m	4.485ms	500	500	100.00
V2	err	csrng_err	19.000s	25.241us	500	500	100.00
V2	cmds	csrng_cmds	8.183m	38.001ms	50	50	100.00
V2	life cycle	csrng_cmds	8.183m	38.001ms	50	50	100.00
V2	stress_all	csrng_stress_all	32.717m	65.589ms	50	50	100.00
V2	intr_test	csrng_intr_test	7.000s	137.878us	50	50	100.00
V2	alert_test	csrng_alert_test	8.000s	120.546us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	13.000s	269.298us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	13.000s	269.298us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	7.000s	112.311us	5	5	100.00
		csrng_csr_rw	6.000s	117.833us	20	20	100.00
		csrng_csr_aliasing	12.000s	330.019us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	308.377us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	7.000s	112.311us	5	5	100.00
		csrng_csr_rw	6.000s	117.833us	20	20	100.00
		csrng_csr_aliasing	12.000s	330.019us	5	5	100.00
		csrng_same_csr_outstanding	8.000s	308.377us	20	20	100.00
V2		TOTAL			1440	1440	100.00
V2S	tl_intg_err	csrng_sec_cm	14.000s	362.757us	5	5	100.00
		csrng_tl_intg_err	14.000s	109.890us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	6.000s	42.121us	50	50	100.00
		csrng_csr_rw	6.000s	117.833us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.883m	4.485ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	32.717m	65.589ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	42.000s	1.755ms	200	200	100.00
		csrng_err	19.000s	25.241us	500	500	100.00
		csrng_sec_cm	14.000s	362.757us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	42.000s	1.755ms	200	200	100.00
		csrng_err	19.000s	25.241us	500	500	100.00
		csrng_sec_cm	14.000s	362.757us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	42.000s	1.755ms	200	200	100.00
		csrng_err	19.000s	25.241us	500	500	100.00
		csrng_sec_cm	14.000s	362.757us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	42.000s	1.755ms	200	200	100.00
		csrng_err	19.000s	25.241us	500	500	100.00
		csrng_sec_cm	14.000s	362.757us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	42.000s	1.755ms	200	200	100.00
		csrng_err	19.000s	25.241us	500	500	100.00
		csrng_sec_cm	14.000s	362.757us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	42.000s	1.755ms	200	200	100.00
		csrng_err	19.000s	25.241us	500	500	100.00
		csrng_sec_cm	14.000s	362.757us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	42.000s	1.755ms	200	200	100.00
		csrng_err	19.000s	25.241us	500	500	100.00
		csrng_sec_cm	14.000s	362.757us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.883m	4.485ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	42.000s	1.755ms	200	200	100.00
		csrng_err	19.000s	25.241us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	32.717m	65.589ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.883m	4.485ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	109.890us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	42.000s	1.755ms	200	200	100.00
		csrng_err	19.000s	25.241us	500	500	100.00
		csrng_sec_cm	14.000s	362.757us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	42.000s	1.755ms	200	200	100.00
		csrng_err	19.000s	25.241us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	42.000s	1.755ms	200	200	100.00
		csrng_err	19.000s	25.241us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	42.000s	1.755ms	200	200	100.00
		csrng_err	19.000s	25.241us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	42.000s	1.755ms	200	200	100.00
		csrng_err	19.000s	25.241us	500	500	100.00
		csrng_sec_cm	14.000s	362.757us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	42.000s	1.755ms	200	200	100.00
		csrng_err	19.000s	25.241us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	3.067m	10.031ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1620	1630	99.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	9	9	9	100.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.37	98.39	96.21	99.12	96.70	91.90	100.00	97.41	90.76

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:868) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
  • Test csrng_stress_all_with_rand_reset has 9 failures.

    • 0.csrng_stress_all_with_rand_reset.55545260381946713896556915000945313309794345055233302819939869776097036828957
      Line 103, in log /workspaces/repo/scratch/os_regression_2024_10_02/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4066226686 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4066226686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.csrng_stress_all_with_rand_reset.98391310656458614526553160203491564232739320804589912538192464214028411795845
      Line 98, in log /workspaces/repo/scratch/os_regression_2024_10_02/csrng-sim-xcelium/2.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 867292765 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 867292765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 7 more failures.

• UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 1.csrng_stress_all_with_rand_reset.62506306219018752246579889909104432021776974654461628892627132525049822472961
      Line 106, in log /workspaces/repo/scratch/os_regression_2024_10_02/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @   4064216 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
        UVM_INFO @   4064216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.09.25_10.59.15
• 2024.09.19_09.03.06
• 2024.09.12_10.14.43
• 2024.09.10_08.09.39
• 2024.09.05_04.19.11
• 2024.09.02_11.28.59