EDN Simulation Results

Friday May 26 2023 07:06:59 UTC

GitHub Revision: `213e792ea`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2340441291

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.940s	15.657us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.920s	132.312us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.920s	32.583us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.890s	992.138us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.370s	64.756us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.750s	187.162us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.920s	32.583us	20	20	100.00
		edn_csr_aliasing	1.370s	64.756us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.490s	137.587us	50	50	100.00
V2	csrng_commands	edn_genbits	1.490s	137.587us	50	50	100.00
V2	genbits	edn_genbits	1.490s	137.587us	50	50	100.00
V2	interrupts	edn_intr	1.130s	21.044us	50	50	100.00
V2	alerts	edn_alert	1.060s	72.863us	50	50	100.00
V2	errs	edn_err	1.140s	19.538us	50	50	100.00
V2	disable	edn_disable	0.970s	34.353us	45	50	90.00
		edn_disable_auto_req_mode	1.080s	24.551us	50	50	100.00
V2	stress_all	edn_stress_all	3.950s	379.579us	50	50	100.00
V2	intr_test	edn_intr_test	0.940s	24.987us	50	50	100.00
V2	alert_test	edn_alert_test	2.150s	107.887us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.730s	195.855us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.730s	195.855us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.920s	132.312us	5	5	100.00
		edn_csr_rw	0.920s	32.583us	20	20	100.00
		edn_csr_aliasing	1.370s	64.756us	5	5	100.00
		edn_same_csr_outstanding	1.490s	191.375us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.920s	132.312us	5	5	100.00
		edn_csr_rw	0.920s	32.583us	20	20	100.00
		edn_csr_aliasing	1.370s	64.756us	5	5	100.00
		edn_same_csr_outstanding	1.490s	191.375us	20	20	100.00
V2		TOTAL			485	490	98.98
V2S	tl_intg_err	edn_sec_cm	6.990s	1.842ms	5	5	100.00
		edn_tl_intg_err	6.610s	410.184us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.960s	15.118us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.060s	72.863us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.990s	1.842ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.990s	1.842ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.990s	1.842ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.060s	72.863us	50	50	100.00
		edn_sec_cm	6.990s	1.842ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.060s	72.863us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	6.610s	410.184us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	50.630m	132.888ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			675	680	99.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.22	99.03	94.16	96.79	73.03	98.62	99.77	98.14

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 5 failures:

Test edn_disable has 5 failures.

1.edn_disable.3699320324
Line 222, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_disable/latest/run.log

  UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.edn_disable.2880864514
Line 222, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/17.edn_disable/latest/run.log

  UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.