748235cbb6| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 0.970s | 17.340us | 48 | 50 | 96.00 |
| V1 | csr_hw_reset | edn_csr_hw_reset | 0.940s | 18.703us | 5 | 5 | 100.00 |
| V1 | csr_rw | edn_csr_rw | 0.890s | 11.634us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | edn_csr_bit_bash | 6.030s | 1.048ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | edn_csr_aliasing | 1.100s | 31.833us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 1.740s | 25.921us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 0.890s | 11.634us | 20 | 20 | 100.00 |
| edn_csr_aliasing | 1.100s | 31.833us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 103 | 105 | 98.10 | |||
| V2 | firmware | edn_genbits | 1.919m | 8.812ms | 299 | 300 | 99.67 |
| V2 | csrng_commands | edn_genbits | 1.919m | 8.812ms | 299 | 300 | 99.67 |
| V2 | genbits | edn_genbits | 1.919m | 8.812ms | 299 | 300 | 99.67 |
| V2 | interrupts | edn_intr | 1.140s | 21.239us | 48 | 50 | 96.00 |
| V2 | alerts | edn_alert | 1.070s | 18.860us | 49 | 50 | 98.00 |
| V2 | errs | edn_err | 1.440s | 35.938us | 98 | 100 | 98.00 |
| V2 | disable | edn_disable | 0.960s | 16.016us | 42 | 50 | 84.00 |
| edn_disable_auto_req_mode | 1.200s | 376.299us | 45 | 50 | 90.00 | ||
| V2 | stress_all | edn_stress_all | 4.440s | 416.850us | 45 | 50 | 90.00 |
| V2 | intr_test | edn_intr_test | 0.910s | 17.579us | 50 | 50 | 100.00 |
| V2 | alert_test | edn_alert_test | 0.990s | 21.927us | 46 | 50 | 92.00 |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 3.440s | 553.711us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | edn_tl_errors | 3.440s | 553.711us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 0.940s | 18.703us | 5 | 5 | 100.00 |
| edn_csr_rw | 0.890s | 11.634us | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 1.100s | 31.833us | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 1.420s | 61.434us | 18 | 20 | 90.00 | ||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 0.940s | 18.703us | 5 | 5 | 100.00 |
| edn_csr_rw | 0.890s | 11.634us | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 1.100s | 31.833us | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 1.420s | 61.434us | 18 | 20 | 90.00 | ||
| V2 | TOTAL | 760 | 790 | 96.20 | |||
| V2S | tl_intg_err | edn_sec_cm | 4.260s | 253.390us | 3 | 5 | 60.00 |
| edn_tl_intg_err | 3.560s | 180.225us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | edn_regwen | 0.960s | 15.815us | 9 | 10 | 90.00 |
| V2S | sec_cm_config_mubi | edn_alert | 1.070s | 18.860us | 49 | 50 | 98.00 |
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 4.260s | 253.390us | 3 | 5 | 60.00 |
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 4.260s | 253.390us | 3 | 5 | 60.00 |
| V2S | sec_cm_ctr_redun | edn_sec_cm | 4.260s | 253.390us | 3 | 5 | 60.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 1.070s | 18.860us | 49 | 50 | 98.00 |
| edn_sec_cm | 4.260s | 253.390us | 3 | 5 | 60.00 | ||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 1.070s | 18.860us | 49 | 50 | 98.00 |
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 3.560s | 180.225us | 20 | 20 | 100.00 |
| V2S | TOTAL | 32 | 35 | 91.43 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 42.185m | 418.127ms | 44 | 50 | 88.00 |
| V3 | TOTAL | 44 | 50 | 88.00 | |||
| TOTAL | 939 | 980 | 95.82 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 11 | 11 | 2 | 18.18 |
| V2S | 3 | 3 | 1 | 33.33 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.06 | 99.02 | 92.32 | 96.84 | 93.42 | 98.62 | 99.77 | 99.40 |
Exit reason: Error: User command failed Job returned non-zero exit code has 38 failures:
Test edn_intr has 2 failures.
0.edn_intr.112488686628295305578417457412720194249414146157704457337959400942462032520221
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_intr/latest/run.log
[make]: simulate
cd /workspace/0.edn_intr/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242407965 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_intr.1242407965
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:45 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
7.edn_intr.32519332887685359204024857119726707801446301574010731695803725772549976373581
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/7.edn_intr/latest/run.log
[make]: simulate
cd /workspace/7.edn_intr/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005102413 -assert nopostproc +UVM_TESTNAME=edn_intr_test +UVM_TEST_SEQ=edn_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.edn_intr.3005102413
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:45 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test edn_sec_cm has 2 failures.
0.edn_sec_cm.44875773265206149207147668481269958871922089021607152848222641980101858199730
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_sec_cm/latest/run.log
[make]: simulate
cd /workspace/0.edn_sec_cm/latest && /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738732722 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.edn_sec_cm.3738732722
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:45 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.edn_sec_cm.100757485197100032091459485907851272445932710197671852433798155515228266220040
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/3.edn_sec_cm/latest/run.log
[make]: simulate
cd /workspace/3.edn_sec_cm/latest && /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877709832 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.edn_sec_cm.877709832
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:45 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test edn_same_csr_outstanding has 2 failures.
0.edn_same_csr_outstanding.69319727602197617249197315957310932628778716010572848222019085635118359227412
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_same_csr_outstanding/latest/run.log
[make]: simulate
cd /workspace/0.edn_same_csr_outstanding/latest && /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699064852 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.edn_same_csr_outstanding.1699064852
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:36 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
5.edn_same_csr_outstanding.52354731877121826672275509674695170503562511925253622121930866630048958062533
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/5.edn_same_csr_outstanding/latest/run.log
[make]: simulate
cd /workspace/5.edn_same_csr_outstanding/latest && /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616243141 -assert nopostproc +UVM_TESTNAME=edn_base_test +UVM_TEST_SEQ=edn_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.edn_same_csr_outstanding.616243141
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:36 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test edn_stress_all has 5 failures.
1.edn_stress_all.79510813814524947020786828705069670048463992147248356352752395726814931932665
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_stress_all/latest/run.log
[make]: simulate
cd /workspace/1.edn_stress_all/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037915641 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_stress_all.1037915641
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:45 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
6.edn_stress_all.4245894080480677492375662738003487124122416731141367101124961346863232359201
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/6.edn_stress_all/latest/run.log
[make]: simulate
cd /workspace/6.edn_stress_all/latest && /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829856545 -assert nopostproc +UVM_TESTNAME=edn_stress_all_test +UVM_TEST_SEQ=edn_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.edn_stress_all.829856545
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:45 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more failures.
Test edn_disable has 7 failures.
1.edn_disable.108470615143355584340833289618536961872298084047877884931950298919369395733482
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_disable/latest/run.log
[make]: simulate
cd /workspace/1.edn_disable/latest && /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984496618 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.edn_disable.1984496618
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:45 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
11.edn_disable.70379827095021908804754862337116515044353448310377061697139380219887379960492
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/11.edn_disable/latest/run.log
[make]: simulate
cd /workspace/11.edn_disable/latest && /workspace/default/simv +test_timeout_ns=100_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780713644 -assert nopostproc +UVM_TESTNAME=edn_disable_test +UVM_TEST_SEQ=edn_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.edn_disable.2780713644
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 3 12:45 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 5 more failures.
... and 7 more tests.
Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
Test edn_genbits has 1 failures.
1.edn_genbits.3620530505024794308948039705399170830034262762879608815642553741821955782412
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_genbits/latest/run.log
Job ID: smart:1c1a8bb9-5d89-45fb-912e-26d1b2f54f5d
Test edn_stress_all_with_rand_reset has 1 failures.
49.edn_stress_all_with_rand_reset.60069934016381224701877921516381028259184925721941174240270880485575041136370
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/49.edn_stress_all_with_rand_reset/latest/run.log
Job ID: smart:e16d781c-e34f-4c10-9259-f732abd46f2b
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
31.edn_disable.37495114074411190922335751825404531868713479642412140106666259797192435543423
Line 255, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/31.edn_disable/latest/run.log
UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---