EDN Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.090s 18.282us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.000s 26.480us 5 5 100.00
V1 csr_rw edn_csr_rw 1.050s 29.397us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.660s 503.787us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.700s 183.591us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.160s 114.531us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.050s 29.397us 20 20 100.00
edn_csr_aliasing 1.700s 183.591us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.952m 8.744ms 300 300 100.00
V2 csrng_commands edn_genbits 1.952m 8.744ms 300 300 100.00
V2 genbits edn_genbits 1.952m 8.744ms 300 300 100.00
V2 interrupts edn_intr 1.240s 22.380us 50 50 100.00
V2 alerts edn_alert 1.460s 90.327us 200 200 100.00
V2 errs edn_err 1.510s 36.876us 100 100 100.00
V2 disable edn_disable 0.960s 15.358us 50 50 100.00
edn_disable_auto_req_mode 1.620s 42.649us 50 50 100.00
V2 stress_all edn_stress_all 6.960s 714.310us 50 50 100.00
V2 intr_test edn_intr_test 1.100s 30.125us 50 50 100.00
V2 alert_test edn_alert_test 1.090s 19.422us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.280s 686.428us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.280s 686.428us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.000s 26.480us 5 5 100.00
edn_csr_rw 1.050s 29.397us 20 20 100.00
edn_csr_aliasing 1.700s 183.591us 5 5 100.00
edn_same_csr_outstanding 1.410s 104.283us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.000s 26.480us 5 5 100.00
edn_csr_rw 1.050s 29.397us 20 20 100.00
edn_csr_aliasing 1.700s 183.591us 5 5 100.00
edn_same_csr_outstanding 1.410s 104.283us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.230s 4.518ms 5 5 100.00
edn_tl_intg_err 5.190s 596.074us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.190s 18.385us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.460s 90.327us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.230s 4.518ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.230s 4.518ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.230s 4.518ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.230s 4.518ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.460s 90.327us 200 200 100.00
edn_sec_cm 9.230s 4.518ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.460s 90.327us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 5.190s 596.074us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 44.334m 111.820ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.69 98.25 93.91 97.02 92.44 96.37 99.77 92.08

Past Results