EDN Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: 3e0219a2c5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.060s 16.104us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.960s 16.888us 5 5 100.00
V1 csr_rw edn_csr_rw 0.960s 19.539us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.340s 172.477us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.490s 72.465us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.020s 137.053us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.960s 19.539us 20 20 100.00
edn_csr_aliasing 1.490s 72.465us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 4.510s 781.680us 300 300 100.00
V2 csrng_commands edn_genbits 4.510s 781.680us 300 300 100.00
V2 genbits edn_genbits 4.510s 781.680us 300 300 100.00
V2 interrupts edn_intr 1.230s 23.255us 50 50 100.00
V2 alerts edn_alert 1.550s 404.844us 200 200 100.00
V2 errs edn_err 1.330s 31.079us 100 100 100.00
V2 disable edn_disable 0.960s 41.014us 50 50 100.00
edn_disable_auto_req_mode 1.520s 45.565us 50 50 100.00
V2 stress_all edn_stress_all 7.860s 417.471us 50 50 100.00
V2 intr_test edn_intr_test 0.930s 16.628us 50 50 100.00
V2 alert_test edn_alert_test 1.140s 24.398us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.960s 421.152us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.960s 421.152us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.960s 16.888us 5 5 100.00
edn_csr_rw 0.960s 19.539us 20 20 100.00
edn_csr_aliasing 1.490s 72.465us 5 5 100.00
edn_same_csr_outstanding 1.540s 77.809us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.960s 16.888us 5 5 100.00
edn_csr_rw 0.960s 19.539us 20 20 100.00
edn_csr_aliasing 1.490s 72.465us 5 5 100.00
edn_same_csr_outstanding 1.540s 77.809us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 8.460s 1.020ms 5 5 100.00
edn_tl_intg_err 2.620s 101.525us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.020s 18.829us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.550s 404.844us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 8.460s 1.020ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 8.460s 1.020ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 8.460s 1.020ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 8.460s 1.020ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.550s 404.844us 200 200 100.00
edn_sec_cm 8.460s 1.020ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.550s 404.844us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.620s 101.525us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 43.117m 225.239ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.83 98.25 93.85 91.61 91.86 96.37 99.77 92.08

Past Results