EDN Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.050s 17.920us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.980s 17.392us 5 5 100.00
V1 csr_rw edn_csr_rw 1.010s 31.411us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.790s 134.259us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.530s 152.399us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.070s 167.170us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.010s 31.411us 20 20 100.00
edn_csr_aliasing 1.530s 152.399us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 2.030m 9.067ms 300 300 100.00
V2 csrng_commands edn_genbits 2.030m 9.067ms 300 300 100.00
V2 genbits edn_genbits 2.030m 9.067ms 300 300 100.00
V2 interrupts edn_intr 1.280s 22.326us 50 50 100.00
V2 alerts edn_alert 1.760s 441.615us 200 200 100.00
V2 errs edn_err 1.350s 24.956us 100 100 100.00
V2 disable edn_disable 1.040s 10.881us 50 50 100.00
edn_disable_auto_req_mode 1.540s 37.423us 50 50 100.00
V2 stress_all edn_stress_all 7.420s 341.649us 50 50 100.00
V2 intr_test edn_intr_test 0.980s 176.142us 50 50 100.00
V2 alert_test edn_alert_test 1.230s 31.849us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.500s 509.838us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.500s 509.838us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.980s 17.392us 5 5 100.00
edn_csr_rw 1.010s 31.411us 20 20 100.00
edn_csr_aliasing 1.530s 152.399us 5 5 100.00
edn_same_csr_outstanding 1.600s 138.788us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.980s 17.392us 5 5 100.00
edn_csr_rw 1.010s 31.411us 20 20 100.00
edn_csr_aliasing 1.530s 152.399us 5 5 100.00
edn_same_csr_outstanding 1.600s 138.788us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 5.050s 1.185ms 5 5 100.00
edn_tl_intg_err 3.820s 157.568us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.000s 15.388us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.760s 441.615us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 5.050s 1.185ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 5.050s 1.185ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 5.050s 1.185ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 5.050s 1.185ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.760s 441.615us 200 200 100.00
edn_sec_cm 5.050s 1.185ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.760s 441.615us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.820s 157.568us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 56.613m 209.425ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.55 98.25 93.91 96.97 91.28 96.37 99.77 92.28

Past Results