EDN Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: 0bfa990ddc

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.060s 17.592us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.920s 32.908us 5 5 100.00
V1 csr_rw edn_csr_rw 0.990s 16.848us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.320s 257.608us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.530s 143.175us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.750s 56.835us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.990s 16.848us 20 20 100.00
edn_csr_aliasing 1.530s 143.175us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 2.052m 9.102ms 299 300 99.67
V2 csrng_commands edn_genbits 2.052m 9.102ms 299 300 99.67
V2 genbits edn_genbits 2.052m 9.102ms 299 300 99.67
V2 interrupts edn_intr 1.170s 22.082us 50 50 100.00
V2 alerts edn_alert 1.370s 29.959us 200 200 100.00
V2 errs edn_err 1.440s 33.999us 100 100 100.00
V2 disable edn_disable 0.940s 14.781us 50 50 100.00
edn_disable_auto_req_mode 1.410s 43.273us 50 50 100.00
V2 stress_all edn_stress_all 7.440s 397.765us 50 50 100.00
V2 intr_test edn_intr_test 0.970s 18.702us 50 50 100.00
V2 alert_test edn_alert_test 3.560s 204.475us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.130s 358.376us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.130s 358.376us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.920s 32.908us 5 5 100.00
edn_csr_rw 0.990s 16.848us 20 20 100.00
edn_csr_aliasing 1.530s 143.175us 5 5 100.00
edn_same_csr_outstanding 1.500s 67.372us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.920s 32.908us 5 5 100.00
edn_csr_rw 0.990s 16.848us 20 20 100.00
edn_csr_aliasing 1.530s 143.175us 5 5 100.00
edn_same_csr_outstanding 1.500s 67.372us 20 20 100.00
V2 TOTAL 939 940 99.89
V2S tl_intg_err edn_sec_cm 9.860s 644.766us 5 5 100.00
edn_tl_intg_err 3.940s 198.721us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.060s 17.762us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.370s 29.959us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.860s 644.766us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.860s 644.766us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.860s 644.766us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.860s 644.766us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.370s 29.959us 200 200 100.00
edn_sec_cm 9.860s 644.766us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.370s 29.959us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.940s 198.721us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 1.135h 2.217s 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1129 1130 99.91

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 10 90.91
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.67 98.25 93.97 97.02 92.44 96.37 99.77 91.89

Failure Buckets

Past Results