EDN Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.100s	18.365us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.950s	31.295us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.010s	16.509us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.510s	1.778ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.260s	18.050us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.680s	101.356us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.010s	16.509us	20	20	100.00
		edn_csr_aliasing	1.260s	18.050us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	7.870s	1.039ms	300	300	100.00
V2	csrng_commands	edn_genbits	7.870s	1.039ms	300	300	100.00
V2	genbits	edn_genbits	7.870s	1.039ms	300	300	100.00
V2	interrupts	edn_intr	1.280s	32.325us	50	50	100.00
V2	alerts	edn_alert	1.480s	27.901us	200	200	100.00
V2	errs	edn_err	1.450s	29.848us	100	100	100.00
V2	disable	edn_disable	7.990s	500.000us	49	50	98.00
		edn_disable_auto_req_mode	1.540s	49.637us	50	50	100.00
V2	stress_all	edn_stress_all	8.230s	424.492us	50	50	100.00
V2	intr_test	edn_intr_test	0.950s	17.094us	50	50	100.00
V2	alert_test	edn_alert_test	1.750s	70.886us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.030s	123.379us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.030s	123.379us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.950s	31.295us	5	5	100.00
		edn_csr_rw	1.010s	16.509us	20	20	100.00
		edn_csr_aliasing	1.260s	18.050us	5	5	100.00
		edn_same_csr_outstanding	1.520s	69.695us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.950s	31.295us	5	5	100.00
		edn_csr_rw	1.010s	16.509us	20	20	100.00
		edn_csr_aliasing	1.260s	18.050us	5	5	100.00
		edn_same_csr_outstanding	1.520s	69.695us	20	20	100.00
V2		TOTAL			939	940	99.89
V2S	tl_intg_err	edn_sec_cm	7.690s	895.837us	5	5	100.00
		edn_tl_intg_err	8.170s	477.698us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.010s	25.112us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.480s	27.901us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.690s	895.837us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.690s	895.837us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.690s	895.837us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.690s	895.837us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.480s	27.901us	200	200	100.00
		edn_sec_cm	7.690s	895.837us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.480s	27.901us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	8.170s	477.698us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	55.676m	281.390ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1129	1130	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.52	98.25	93.91	97.02	91.28	96.37	99.77	92.06

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_disable has 1 failures.

    • 11.edn_disable.113009804816037108532915628342518101879281120860744311893515132073903419352959
      Line 259, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/11.edn_disable/latest/run.log

        UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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