EDN Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.090s 16.975us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.990s 15.172us 5 5 100.00
V1 csr_rw edn_csr_rw 0.990s 18.802us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.100s 195.736us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.580s 37.415us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.910s 84.626us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.990s 18.802us 20 20 100.00
edn_csr_aliasing 1.580s 37.415us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.542m 5.006ms 300 300 100.00
V2 csrng_commands edn_genbits 1.542m 5.006ms 300 300 100.00
V2 genbits edn_genbits 1.542m 5.006ms 300 300 100.00
V2 interrupts edn_intr 1.290s 23.214us 50 50 100.00
V2 alerts edn_alert 1.450s 305.810us 200 200 100.00
V2 errs edn_err 1.390s 28.722us 100 100 100.00
V2 disable edn_disable 0.970s 26.564us 50 50 100.00
edn_disable_auto_req_mode 1.540s 49.759us 50 50 100.00
V2 stress_all edn_stress_all 6.290s 337.363us 50 50 100.00
V2 intr_test edn_intr_test 0.990s 16.605us 50 50 100.00
V2 alert_test edn_alert_test 1.160s 24.388us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.610s 144.105us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.610s 144.105us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.990s 15.172us 5 5 100.00
edn_csr_rw 0.990s 18.802us 20 20 100.00
edn_csr_aliasing 1.580s 37.415us 5 5 100.00
edn_same_csr_outstanding 1.510s 485.454us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.990s 15.172us 5 5 100.00
edn_csr_rw 0.990s 18.802us 20 20 100.00
edn_csr_aliasing 1.580s 37.415us 5 5 100.00
edn_same_csr_outstanding 1.510s 485.454us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.130s 2.027ms 5 5 100.00
edn_tl_intg_err 2.890s 117.605us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.050s 34.835us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.450s 305.810us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.130s 2.027ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.130s 2.027ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.130s 2.027ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.130s 2.027ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.450s 305.810us 200 200 100.00
edn_sec_cm 9.130s 2.027ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.450s 305.810us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.890s 117.605us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 39.958m 98.721ms 49 50 98.00
V3 TOTAL 49 50 98.00
TOTAL 1129 1130 99.91

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.70 98.25 93.97 97.02 92.44 96.37 99.77 92.06

Failure Buckets

Past Results