EDN Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: c082b8981f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.100s 20.323us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.980s 16.952us 5 5 100.00
V1 csr_rw edn_csr_rw 0.960s 12.788us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.390s 458.755us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.630s 143.345us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.100s 31.364us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.960s 12.788us 20 20 100.00
edn_csr_aliasing 1.630s 143.345us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.749m 6.666ms 300 300 100.00
V2 csrng_commands edn_genbits 1.749m 6.666ms 300 300 100.00
V2 genbits edn_genbits 1.749m 6.666ms 300 300 100.00
V2 interrupts edn_intr 1.240s 21.437us 50 50 100.00
V2 alerts edn_alert 1.490s 42.436us 200 200 100.00
V2 errs edn_err 1.430s 36.549us 100 100 100.00
V2 disable edn_disable 1.020s 18.398us 50 50 100.00
edn_disable_auto_req_mode 1.500s 48.057us 50 50 100.00
V2 stress_all edn_stress_all 6.740s 370.287us 50 50 100.00
V2 intr_test edn_intr_test 0.940s 16.034us 50 50 100.00
V2 alert_test edn_alert_test 1.240s 37.398us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.000s 424.251us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.000s 424.251us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.980s 16.952us 5 5 100.00
edn_csr_rw 0.960s 12.788us 20 20 100.00
edn_csr_aliasing 1.630s 143.345us 5 5 100.00
edn_same_csr_outstanding 1.410s 172.399us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.980s 16.952us 5 5 100.00
edn_csr_rw 0.960s 12.788us 20 20 100.00
edn_csr_aliasing 1.630s 143.345us 5 5 100.00
edn_same_csr_outstanding 1.410s 172.399us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 13.260s 881.932us 5 5 100.00
edn_tl_intg_err 2.580s 121.412us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.020s 40.962us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.490s 42.436us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 13.260s 881.932us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 13.260s 881.932us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 13.260s 881.932us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 13.260s 881.932us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.490s 42.436us 200 200 100.00
edn_sec_cm 13.260s 881.932us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.490s 42.436us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.580s 121.412us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.884h 10.000s 30 50 60.00
V3 TOTAL 30 50 60.00
TOTAL 1110 1130 98.23

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.69 98.25 93.73 97.02 91.86 96.37 99.77 92.80

Failure Buckets

Past Results