EDN Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Simulator: VCS

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.610s	19.438us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.580s	43.241us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.470s	23.177us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	7.860s	2.085ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	2.370s	43.083us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.410s	23.700us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.470s	23.177us	20	20	100.00
		edn_csr_aliasing	2.370s	43.083us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.661m	5.221ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.661m	5.221ms	300	300	100.00
V2	genbits	edn_genbits	1.661m	5.221ms	300	300	100.00
V2	interrupts	edn_intr	1.820s	21.411us	50	50	100.00
V2	alerts	edn_alert	2.470s	305.744us	200	200	100.00
V2	errs	edn_err	1.970s	27.860us	100	100	100.00
V2	disable	edn_disable	1.440s	11.118us	50	50	100.00
		edn_disable_auto_req_mode	2.240s	46.499us	45	50	90.00
V2	stress_all	edn_stress_all	10.670s	364.282us	50	50	100.00
V2	intr_test	edn_intr_test	1.470s	122.762us	50	50	100.00
V2	alert_test	edn_alert_test	1.530s	32.743us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	5.700s	914.167us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	5.700s	914.167us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.580s	43.241us	5	5	100.00
		edn_csr_rw	1.470s	23.177us	20	20	100.00
		edn_csr_aliasing	2.370s	43.083us	5	5	100.00
		edn_same_csr_outstanding	2.420s	79.573us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.580s	43.241us	5	5	100.00
		edn_csr_rw	1.470s	23.177us	20	20	100.00
		edn_csr_aliasing	2.370s	43.083us	5	5	100.00
		edn_same_csr_outstanding	2.420s	79.573us	20	20	100.00
V2		TOTAL			935	940	99.47
V2S	tl_intg_err	edn_sec_cm	10.390s	644.878us	5	5	100.00
		edn_tl_intg_err	4.190s	107.086us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.570s	20.718us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	2.470s	305.744us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	10.390s	644.878us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	10.390s	644.878us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	10.390s	644.878us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	10.390s	644.878us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.470s	305.744us	200	200	100.00
		edn_sec_cm	10.390s	644.878us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.470s	305.744us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.190s	107.086us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.523m	23.242ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			1105	1130	97.79

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.68	98.23	93.97	97.02	91.28	96.33	99.77	93.18

Failure Buckets

Job timed out after * minutes has 19 failures:
- Test edn_stress_all_with_rand_reset has 19 failures.
  - 1.edn_stress_all_with_rand_reset.74823058211149462473333479823637770572549646502668612096186625433428889562996
    Log /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - 6.edn_stress_all_with_rand_reset.39971483973905562083788676246235305717251566057675685457805143030112112614819
    Log /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - ... and 17 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues

has 5 failures:

Test edn_disable_auto_req_mode has 5 failures.

0.edn_disable_auto_req_mode.82706308794458483783824140555178730674727042920690707865695154587616169394757
Line 72, in log /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/0.edn_disable_auto_req_mode/latest/run.log

  UVM_ERROR @   7152616 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_edn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_edn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @   7152616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.edn_disable_auto_req_mode.18756994273491365893340612700013468489695124961066953497536538058092888496695
Line 72, in log /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/5.edn_disable_auto_req_mode/latest/run.log

  UVM_ERROR @   6622982 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_edn_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_edn_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @   6622982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:771) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test edn_stress_all_with_rand_reset has 1 failures.
  - 45.edn_stress_all_with_rand_reset.1608049941226482220997688980769168361513296342857999671498108825746345673358
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_10_02/edn-sim-vcs/45.edn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  16545580 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  16545580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```