78ad89d1aa| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 29.060s | 49 | 50 | 98.00 | |
| V1 | csr_hw_reset | edn_csr_hw_reset | 1.130s | 42.277us | 5 | 5 | 100.00 |
| V1 | csr_rw | edn_csr_rw | 1.210s | 42.289us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | edn_csr_bit_bash | 6.070s | 259.816us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | edn_csr_aliasing | 1.400s | 35.024us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 2.290s | 117.045us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 1.210s | 42.289us | 20 | 20 | 100.00 |
| edn_csr_aliasing | 1.400s | 35.024us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 104 | 105 | 99.05 | |||
| V2 | firmware | edn_genbits | 29.019s | 292 | 300 | 97.33 | |
| V2 | csrng_commands | edn_genbits | 29.019s | 292 | 300 | 97.33 | |
| V2 | genbits | edn_genbits | 29.019s | 292 | 300 | 97.33 | |
| V2 | interrupts | edn_intr | 37.475s | 48 | 50 | 96.00 | |
| V2 | alerts | edn_alert | 22.597s | 197 | 200 | 98.50 | |
| V2 | errs | edn_err | 31.782s | 97 | 100 | 97.00 | |
| V2 | disable | edn_disable | 31.743s | 49 | 50 | 98.00 | |
| edn_disable_auto_req_mode | 2.090s | 44.549us | 49 | 50 | 98.00 | ||
| V2 | stress_all | edn_stress_all | 8.600s | 419.866us | 50 | 50 | 100.00 |
| V2 | intr_test | edn_intr_test | 1.230s | 12.838us | 50 | 50 | 100.00 |
| V2 | alert_test | edn_alert_test | 2.090s | 94.455us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 4.330s | 2.706ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | edn_tl_errors | 4.330s | 2.706ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 1.130s | 42.277us | 5 | 5 | 100.00 |
| edn_csr_rw | 1.210s | 42.289us | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 1.400s | 35.024us | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 1.540s | 34.059us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 1.130s | 42.277us | 5 | 5 | 100.00 |
| edn_csr_rw | 1.210s | 42.289us | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 1.400s | 35.024us | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 1.540s | 34.059us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 922 | 940 | 98.09 | |||
| V2S | tl_intg_err | edn_sec_cm | 10.090s | 2.577ms | 5 | 5 | 100.00 |
| edn_tl_intg_err | 6.870s | 426.737us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | edn_regwen | 1.390s | 74.602us | 10 | 10 | 100.00 |
| V2S | sec_cm_config_mubi | edn_alert | 22.597s | 197 | 200 | 98.50 | |
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 10.090s | 2.577ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 10.090s | 2.577ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fifo_ctr_redun | edn_sec_cm | 10.090s | 2.577ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | edn_sec_cm | 10.090s | 2.577ms | 5 | 5 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 22.597s | 197 | 200 | 98.50 | |
| edn_sec_cm | 10.090s | 2.577ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 22.597s | 197 | 200 | 98.50 | |
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 6.870s | 426.737us | 20 | 20 | 100.00 |
| V2S | TOTAL | 35 | 35 | 100.00 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 2.602m | 33.893ms | 28 | 50 | 56.00 |
| V3 | TOTAL | 28 | 50 | 56.00 | |||
| TOTAL | 1089 | 1130 | 96.37 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 11 | 11 | 5 | 45.45 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.95 | 98.23 | 93.91 | 97.02 | 93.60 | 96.33 | 99.77 | 92.80 |
Job timed out after * minutes has 21 failures:
0.edn_stress_all_with_rand_reset.12961843986297865644468034848434769928586101133006514071434597910539906252194
Log /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log
Job timed out after 180 minutes
1.edn_stress_all_with_rand_reset.51661286704235498203173047186541633201328135123080196083953455408242986262295
Log /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log
Job timed out after 180 minutes
... and 19 more failures.
Job returned non-zero exit code has 19 failures:
Test edn_stress_all_with_rand_reset has 1 failures.
8.edn_stress_all_with_rand_reset.4945366951837272626083892767273652916327924086855007945126150158597285576835
Log /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_stress_all_with_rand_reset/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 24 08:48 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
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Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test edn_intr has 2 failures.
8.edn_intr.38640521639793759439380496162923872645001359882118593847202335186212478703178
Log /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_intr/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 24 08:48 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
12.edn_intr.74539966114613812883292419043918888217606066061251461911690914760253904240361
Log /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/12.edn_intr/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 24 08:48 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test edn_err has 3 failures.
8.edn_err.53531480509817233340354304650837093841713163984008492982900502076213508699710
Log /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_err/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 24 08:48 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
98.edn_err.28346461875252689310089755671485769775906680989214442908953515096938234493738
Log /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/98.edn_err/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 24 08:51 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
... and 1 more failures.
Test edn_disable has 1 failures.
8.edn_disable.2164321413709987728272950067314400054555116849798844417727620203466412676759
Log /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/8.edn_disable/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 24 08:48 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test edn_smoke has 1 failures.
10.edn_smoke.13567938493073752473420207483339106514468953180258310261966865679164941180294
Log /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/10.edn_smoke/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Sep 24 08:48 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
... and 2 more tests.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
36.edn_disable_auto_req_mode.34210963160684500404539876209666095544702534223368609691714138512594856911021
Line 72, in log /workspaces/repo/scratch/os_regression_2024_09_23/edn-sim-vcs/36.edn_disable_auto_req_mode/latest/run.log
UVM_FATAL @ 500000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 500000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---