EDN Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: 7e34e67ade

Branch: os_regression_2024_09_17

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.700s 27.423us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.990s 20.833us 5 5 100.00
V1 csr_rw edn_csr_rw 0.960s 11.164us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.040s 229.170us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.340s 25.259us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.490s 50.323us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.960s 11.164us 20 20 100.00
edn_csr_aliasing 1.340s 25.259us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 2.190m 8.770ms 300 300 100.00
V2 csrng_commands edn_genbits 2.190m 8.770ms 300 300 100.00
V2 genbits edn_genbits 2.190m 8.770ms 300 300 100.00
V2 interrupts edn_intr 1.720s 21.273us 50 50 100.00
V2 alerts edn_alert 2.080s 292.582us 200 200 100.00
V2 errs edn_err 1.950s 25.272us 100 100 100.00
V2 disable edn_disable 1.420s 87.500us 50 50 100.00
edn_disable_auto_req_mode 2.000s 37.499us 50 50 100.00
V2 stress_all edn_stress_all 11.140s 387.598us 50 50 100.00
V2 intr_test edn_intr_test 1.030s 26.501us 50 50 100.00
V2 alert_test edn_alert_test 1.500s 55.661us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.950s 897.207us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.950s 897.207us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.990s 20.833us 5 5 100.00
edn_csr_rw 0.960s 11.164us 20 20 100.00
edn_csr_aliasing 1.340s 25.259us 5 5 100.00
edn_same_csr_outstanding 1.320s 110.731us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.990s 20.833us 5 5 100.00
edn_csr_rw 0.960s 11.164us 20 20 100.00
edn_csr_aliasing 1.340s 25.259us 5 5 100.00
edn_same_csr_outstanding 1.320s 110.731us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 11.770s 7.717ms 5 5 100.00
edn_tl_intg_err 5.100s 942.671us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.520s 19.118us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.080s 292.582us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 11.770s 7.717ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 11.770s 7.717ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 11.770s 7.717ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 11.770s 7.717ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.080s 292.582us 200 200 100.00
edn_sec_cm 11.770s 7.717ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.080s 292.582us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 5.100s 942.671us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 3.250m 65.224ms 36 50 72.00
V3 TOTAL 36 50 72.00
TOTAL 1116 1130 98.76

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.64 98.23 93.97 97.07 91.28 96.33 99.77 92.80

Failure Buckets

Past Results