EDN Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: `8a1401d614`

Branch: os_regression_2024_10_11

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.490s	18.593us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.460s	17.173us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.410s	13.912us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.400s	922.980us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.780s	129.935us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.440s	200.239us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.410s	13.912us	20	20	100.00
		edn_csr_aliasing	1.780s	129.935us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	42.933s		290	300	96.67
V2	csrng_commands	edn_genbits	42.933s		290	300	96.67
V2	genbits	edn_genbits	42.933s		290	300	96.67
V2	interrupts	edn_intr	1.630s	26.098us	50	50	100.00
V2	alerts	edn_alert	2.000s	55.970us	200	200	100.00
V2	errs	edn_err	1.980s	30.229us	100	100	100.00
V2	disable	edn_disable	1.360s	15.594us	50	50	100.00
		edn_disable_auto_req_mode	2.230s	56.334us	50	50	100.00
V2	stress_all	edn_stress_all	8.360s	450.109us	50	50	100.00
V2	intr_test	edn_intr_test	1.440s	26.433us	50	50	100.00
V2	alert_test	edn_alert_test	1.490s	80.951us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	5.290s	364.233us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	5.290s	364.233us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.460s	17.173us	5	5	100.00
		edn_csr_rw	1.410s	13.912us	20	20	100.00
		edn_csr_aliasing	1.780s	129.935us	5	5	100.00
		edn_same_csr_outstanding	1.970s	119.195us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.460s	17.173us	5	5	100.00
		edn_csr_rw	1.410s	13.912us	20	20	100.00
		edn_csr_aliasing	1.780s	129.935us	5	5	100.00
		edn_same_csr_outstanding	1.970s	119.195us	20	20	100.00
V2		TOTAL			930	940	98.94
V2S	tl_intg_err	edn_sec_cm	9.020s	2.117ms	5	5	100.00
		edn_tl_intg_err	13.030s	892.113us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.500s	20.852us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	2.000s	55.970us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	9.020s	2.117ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	9.020s	2.117ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	9.020s	2.117ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	9.020s	2.117ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.000s	55.970us	200	200	100.00
		edn_sec_cm	9.020s	2.117ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.000s	55.970us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	13.030s	892.113us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.824m	27.677ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1095	1130	96.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.53	98.23	93.85	97.02	90.70	96.33	99.77	92.80

Failure Buckets

Job timed out after * minutes has 25 failures:
- Test edn_stress_all_with_rand_reset has 25 failures.
  - 1.edn_stress_all_with_rand_reset.82458747970202552983128534325322113815249472552388180305572355089878865082171
    Log /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - 2.edn_stress_all_with_rand_reset.37695078429738512011908125572706579581827215493033841772741079610718230452250
    Log /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - ... and 23 more failures.

Job returned non-zero exit code has 10 failures:

Test edn_genbits has 10 failures.

269.edn_genbits.76300509478022834109517966601870268266892594843448271258221937078681984110505
Log /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/269.edn_genbits/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 12 14:18 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

270.edn_genbits.26267290222551862373162462317215119251538398282143419214287999644197509854007
Log /workspaces/repo/scratch/os_regression_2024_10_11/edn-sim-vcs/270.edn_genbits/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 12 14:18 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 8 more failures.