EDN Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: 29d22a60a2

Branch: os_regression_2024_10_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.520s 22.283us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.300s 19.896us 5 5 100.00
V1 csr_rw edn_csr_rw 1.410s 18.286us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.830s 666.376us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.050s 35.720us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.170s 100.500us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.410s 18.286us 20 20 100.00
edn_csr_aliasing 2.050s 35.720us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 2.704m 13.748ms 300 300 100.00
V2 csrng_commands edn_genbits 2.704m 13.748ms 300 300 100.00
V2 genbits edn_genbits 2.704m 13.748ms 300 300 100.00
V2 interrupts edn_intr 1.860s 22.097us 50 50 100.00
V2 alerts edn_alert 2.600s 396.558us 200 200 100.00
V2 errs edn_err 2.050s 28.883us 100 100 100.00
V2 disable edn_disable 1.420s 11.919us 50 50 100.00
edn_disable_auto_req_mode 2.170s 49.769us 50 50 100.00
V2 stress_all edn_stress_all 9.070s 308.284us 50 50 100.00
V2 intr_test edn_intr_test 1.360s 16.400us 50 50 100.00
V2 alert_test edn_alert_test 1.630s 28.167us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.770s 442.529us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.770s 442.529us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.300s 19.896us 5 5 100.00
edn_csr_rw 1.410s 18.286us 20 20 100.00
edn_csr_aliasing 2.050s 35.720us 5 5 100.00
edn_same_csr_outstanding 1.640s 24.536us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.300s 19.896us 5 5 100.00
edn_csr_rw 1.410s 18.286us 20 20 100.00
edn_csr_aliasing 2.050s 35.720us 5 5 100.00
edn_same_csr_outstanding 1.640s 24.536us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 11.570s 804.847us 5 5 100.00
edn_tl_intg_err 2.770s 784.953us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.430s 41.400us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.600s 396.558us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 11.570s 804.847us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 11.570s 804.847us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 11.570s 804.847us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 11.570s 804.847us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.600s 396.558us 200 200 100.00
edn_sec_cm 11.570s 804.847us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.600s 396.558us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.770s 784.953us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.255m 37.399ms 32 50 64.00
V3 TOTAL 32 50 64.00
TOTAL 1112 1130 98.41

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.94 98.23 93.97 97.07 93.02 96.33 99.77 93.18

Failure Buckets

Past Results