ENTROPY_SRC Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: 69c572b503

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 30.197us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 26.223us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 43.771us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 16.000s 786.585us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 7.000s 419.192us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 32.566us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 43.771us 20 20 100.00
entropy_src_csr_aliasing 7.000s 419.192us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 30.197us 50 50 100.00
entropy_src_rng 4.650m 10.055ms 300 300 100.00
entropy_src_fw_ov 2.450m 5.064ms 294 300 98.00
V2 firmware_mode entropy_src_fw_ov 2.450m 5.064ms 294 300 98.00
V2 rng_mode entropy_src_rng 4.650m 10.055ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 9.000m 10.032ms 386 400 96.50
V2 health_checks entropy_src_rng 4.650m 10.055ms 300 300 100.00
V2 conditioning entropy_src_rng 4.650m 10.055ms 300 300 100.00
V2 interrupts entropy_src_rng 4.650m 10.055ms 300 300 100.00
V2 alerts entropy_src_rng 4.650m 10.055ms 300 300 100.00
entropy_src_functional_alerts 5.000s 59.369us 50 50 100.00
V2 stress_all entropy_src_stress_all 9.000s 317.697us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.817m 10.013ms 961 1000 96.10
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 25.000s 965.448us 50 50 100.00
V2 intr_test entropy_src_intr_test 8.000s 17.204us 50 50 100.00
V2 alert_test entropy_src_alert_test 4.000s 66.941us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 139.330us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 139.330us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 26.223us 5 5 100.00
entropy_src_csr_rw 4.000s 43.771us 20 20 100.00
entropy_src_csr_aliasing 7.000s 419.192us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 244.999us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 26.223us 5 5 100.00
entropy_src_csr_rw 4.000s 43.771us 20 20 100.00
entropy_src_csr_aliasing 7.000s 419.192us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 244.999us 20 20 100.00
V2 TOTAL 2231 2290 97.42
V2S tl_intg_err entropy_src_sec_cm 4.000s 93.194us 5 5 100.00
entropy_src_tl_intg_err 6.000s 200.834us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.650m 10.055ms 300 300 100.00
entropy_src_cfg_regwen 4.000s 22.189us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.650m 10.055ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.650m 10.055ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.650m 10.055ms 300 300 100.00
entropy_src_fw_ov 2.450m 5.064ms 294 300 98.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.817m 10.013ms 961 1000 96.10
entropy_src_sec_cm 4.000s 93.194us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.817m 10.013ms 961 1000 96.10
entropy_src_sec_cm 4.000s 93.194us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.650m 10.055ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.817m 10.013ms 961 1000 96.10
entropy_src_sec_cm 4.000s 93.194us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.817m 10.013ms 961 1000 96.10
entropy_src_sec_cm 4.000s 93.194us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.817m 10.013ms 961 1000 96.10
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 59.369us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 6.000s 200.834us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 5.000m 10.065ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 24.000s 1.016ms 44 50 88.00
TOTAL 2505 2570 97.47

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 8 72.73
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.43 98.17 95.37 98.33 95.84 88.05 96.88 90.46 58.01

Failure Buckets

Past Results