ENTROPY_SRC Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 33.663us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 8.000s 130.446us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 8.000s 52.669us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 20.000s 785.668us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 229.262us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 13.000s 33.271us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 8.000s 52.669us 20 20 100.00
entropy_src_csr_aliasing 8.000s 229.262us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 33.663us 50 50 100.00
entropy_src_rng 4.633m 10.073ms 300 300 100.00
entropy_src_fw_ov 2.350m 5.037ms 288 300 96.00
V2 firmware_mode entropy_src_fw_ov 2.350m 5.037ms 288 300 96.00
V2 rng_mode entropy_src_rng 4.633m 10.073ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 8.883m 10.016ms 383 400 95.75
V2 health_checks entropy_src_rng 4.633m 10.073ms 300 300 100.00
V2 conditioning entropy_src_rng 4.633m 10.073ms 300 300 100.00
V2 interrupts entropy_src_rng 4.633m 10.073ms 300 300 100.00
V2 alerts entropy_src_rng 4.633m 10.073ms 300 300 100.00
entropy_src_functional_alerts 5.000s 65.057us 50 50 100.00
V2 stress_all entropy_src_stress_all 11.000s 488.447us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 10.283m 10.012ms 973 1000 97.30
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 26.000s 3.325ms 50 50 100.00
V2 intr_test entropy_src_intr_test 13.000s 22.708us 50 50 100.00
V2 alert_test entropy_src_alert_test 4.000s 19.602us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 18.000s 151.489us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 18.000s 151.489us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 8.000s 130.446us 5 5 100.00
entropy_src_csr_rw 8.000s 52.669us 20 20 100.00
entropy_src_csr_aliasing 8.000s 229.262us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 87.929us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 8.000s 130.446us 5 5 100.00
entropy_src_csr_rw 8.000s 52.669us 20 20 100.00
entropy_src_csr_aliasing 8.000s 229.262us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 87.929us 20 20 100.00
V2 TOTAL 2234 2290 97.55
V2S tl_intg_err entropy_src_sec_cm 4.000s 91.641us 5 5 100.00
entropy_src_tl_intg_err 10.000s 252.669us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.633m 10.073ms 300 300 100.00
entropy_src_cfg_regwen 3.000s 36.543us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.633m 10.073ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.633m 10.073ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.633m 10.073ms 300 300 100.00
entropy_src_fw_ov 2.350m 5.037ms 288 300 96.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 10.283m 10.012ms 973 1000 97.30
entropy_src_sec_cm 4.000s 91.641us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 10.283m 10.012ms 973 1000 97.30
entropy_src_sec_cm 4.000s 91.641us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.633m 10.073ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 10.283m 10.012ms 973 1000 97.30
entropy_src_sec_cm 4.000s 91.641us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 10.283m 10.012ms 973 1000 97.30
entropy_src_sec_cm 4.000s 91.641us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 10.283m 10.012ms 973 1000 97.30
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 65.057us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 10.000s 252.669us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.533m 10.062ms 49 50 98.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 49 50 98.00
Unmapped tests entropy_src_intr 36.000s 1.022ms 47 50 94.00
TOTAL 2510 2570 97.67

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 8 72.73
V2S 3 3 3 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.40 98.17 95.37 98.33 95.84 88.10 96.88 90.46 57.85

Failure Buckets

Past Results