ENTROPY_SRC Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: 3fd3528c8c

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 30.870us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 9.000s 28.208us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 8.000s 16.535us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 15.000s 690.370us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 16.000s 76.723us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 9.000s 55.335us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 8.000s 16.535us 20 20 100.00
entropy_src_csr_aliasing 16.000s 76.723us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 30.870us 50 50 100.00
entropy_src_rng 4.850m 10.021ms 298 300 99.33
entropy_src_fw_ov 2.267m 5.058ms 279 300 93.00
V2 firmware_mode entropy_src_fw_ov 2.267m 5.058ms 279 300 93.00
V2 rng_mode entropy_src_rng 4.850m 10.021ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 8.317m 10.027ms 381 400 95.25
V2 health_checks entropy_src_rng 4.850m 10.021ms 298 300 99.33
V2 conditioning entropy_src_rng 4.850m 10.021ms 298 300 99.33
V2 interrupts entropy_src_rng 4.850m 10.021ms 298 300 99.33
V2 alerts entropy_src_rng 4.850m 10.021ms 298 300 99.33
entropy_src_functional_alerts 5.000s 56.260us 50 50 100.00
V2 stress_all entropy_src_stress_all 10.000s 340.202us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 10.033m 10.012ms 971 1000 97.10
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 23.000s 628.072us 50 50 100.00
V2 intr_test entropy_src_intr_test 8.000s 122.836us 50 50 100.00
V2 alert_test entropy_src_alert_test 4.000s 44.829us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 10.000s 268.260us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 10.000s 268.260us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 9.000s 28.208us 5 5 100.00
entropy_src_csr_rw 8.000s 16.535us 20 20 100.00
entropy_src_csr_aliasing 16.000s 76.723us 5 5 100.00
entropy_src_same_csr_outstanding 18.000s 34.567us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 9.000s 28.208us 5 5 100.00
entropy_src_csr_rw 8.000s 16.535us 20 20 100.00
entropy_src_csr_aliasing 16.000s 76.723us 5 5 100.00
entropy_src_same_csr_outstanding 18.000s 34.567us 20 20 100.00
V2 TOTAL 2219 2290 96.90
V2S tl_intg_err entropy_src_sec_cm 4.000s 225.126us 5 5 100.00
entropy_src_tl_intg_err 11.000s 214.061us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.850m 10.021ms 298 300 99.33
entropy_src_cfg_regwen 8.000s 70.804us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.850m 10.021ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 4.850m 10.021ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 4.850m 10.021ms 298 300 99.33
entropy_src_fw_ov 2.267m 5.058ms 279 300 93.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 10.033m 10.012ms 971 1000 97.10
entropy_src_sec_cm 4.000s 225.126us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 10.033m 10.012ms 971 1000 97.10
entropy_src_sec_cm 4.000s 225.126us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.850m 10.021ms 298 300 99.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 10.033m 10.012ms 971 1000 97.10
entropy_src_sec_cm 4.000s 225.126us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 10.033m 10.012ms 971 1000 97.10
entropy_src_sec_cm 4.000s 225.126us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 10.033m 10.012ms 971 1000 97.10
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 56.260us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 11.000s 214.061us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.500m 10.036ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 20.000s 1.389ms 48 50 96.00
TOTAL 2497 2570 97.16

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.48 98.19 95.42 98.36 95.88 88.07 97.92 90.46 58.10

Failure Buckets

Past Results