ENTROPY_SRC Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: be1c4a4f52

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 8.000s 379.589us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 62.232us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 24.586us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 15.000s 1.531ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 213.540us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 47.706us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 24.586us 20 20 100.00
entropy_src_csr_aliasing 8.000s 213.540us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 8.000s 379.589us 50 50 100.00
entropy_src_rng 4.750m 10.022ms 300 300 100.00
entropy_src_fw_ov 2.350m 5.032ms 284 300 94.67
V2 firmware_mode entropy_src_fw_ov 2.350m 5.032ms 284 300 94.67
V2 rng_mode entropy_src_rng 4.750m 10.022ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 8.450m 10.060ms 386 400 96.50
V2 health_checks entropy_src_rng 4.750m 10.022ms 300 300 100.00
V2 conditioning entropy_src_rng 4.750m 10.022ms 300 300 100.00
V2 interrupts entropy_src_rng 4.750m 10.022ms 300 300 100.00
V2 alerts entropy_src_rng 4.750m 10.022ms 300 300 100.00
entropy_src_functional_alerts 9.000s 123.717us 50 50 100.00
V2 stress_all entropy_src_stress_all 17.000s 275.496us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.100m 10.013ms 969 1000 96.90
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 22.000s 1.455ms 50 50 100.00
V2 intr_test entropy_src_intr_test 8.000s 28.305us 50 50 100.00
V2 alert_test entropy_src_alert_test 18.000s 59.623us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 16.000s 141.583us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 16.000s 141.583us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 62.232us 5 5 100.00
entropy_src_csr_rw 4.000s 24.586us 20 20 100.00
entropy_src_csr_aliasing 8.000s 213.540us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 708.848us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 62.232us 5 5 100.00
entropy_src_csr_rw 4.000s 24.586us 20 20 100.00
entropy_src_csr_aliasing 8.000s 213.540us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 708.848us 20 20 100.00
V2 TOTAL 2229 2290 97.34
V2S tl_intg_err entropy_src_sec_cm 4.000s 90.387us 5 5 100.00
entropy_src_tl_intg_err 7.000s 802.253us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.750m 10.022ms 300 300 100.00
entropy_src_cfg_regwen 12.000s 30.444us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.750m 10.022ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.750m 10.022ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.750m 10.022ms 300 300 100.00
entropy_src_fw_ov 2.350m 5.032ms 284 300 94.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.100m 10.013ms 969 1000 96.90
entropy_src_sec_cm 4.000s 90.387us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.100m 10.013ms 969 1000 96.90
entropy_src_sec_cm 4.000s 90.387us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.750m 10.022ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.100m 10.013ms 969 1000 96.90
entropy_src_sec_cm 4.000s 90.387us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.100m 10.013ms 969 1000 96.90
entropy_src_sec_cm 4.000s 90.387us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.100m 10.013ms 969 1000 96.90
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 9.000s 123.717us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 802.253us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.500m 10.046ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 23.000s 843.912us 42 50 84.00
TOTAL 2501 2570 97.32

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 8 72.73
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.64 98.19 95.43 98.36 95.79 88.10 96.88 90.46 58.73

Failure Buckets

Past Results