FLASH_CTRL Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.666m	164.498us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.620s	51.026us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	38.090s	108.330us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.730s	712.424us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.518m	11.715ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	56.770s	4.777ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.460s	122.237us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.730s	712.424us	20	20	100.00
		flash_ctrl_csr_aliasing	56.770s	4.777ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.430s	17.869us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.330s	229.137us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.000s	76.282us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.742m	208.569us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	32.507m	376.154ms	3	3	100.00
		flash_ctrl_hw_rma_reset	20.985m	540.416ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.780s	14.909us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	40.710m	369.090ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.437m	13.397ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	26.620s	399.919us	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	59.119m	287.593ms	4	5	80.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.955m	5.412ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	38.410s	663.665us	37	40	92.50
		flash_ctrl_rw_evict_all_en	36.240s	824.714us	39	40	97.50
		flash_ctrl_re_evict	40.470s	451.123us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.158m	2.050ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.158m	2.050ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	16.154m	13.833ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	25.830s	1.009ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.278m	18.145ms	17	20	85.00
V2	error_mp	flash_ctrl_error_mp	43.888m	25.122ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.020m	4.020ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	37.518m	1.235ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.900s	26.075us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	5.980m	2.538ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.670s	39.321us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.410s	15.532us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	24.707m	262.659us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.345m	21.928ms	50	50	100.00
		flash_ctrl_otp_reset	2.296m	97.753us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	32.507m	376.154ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	6.168m	3.915ms	40	40	100.00
		flash_ctrl_intr_wr	2.018m	23.355ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	10.103m	100.425ms	36	40	90.00
		flash_ctrl_intr_wr_slow_flash	8.754m	192.594ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.566m	3.814ms	14	20	70.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	32.330s	659.746us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.090s	32.302us	5	5	100.00
		flash_ctrl_ro_derr	6.216m	1.809ms	10	10	100.00
		flash_ctrl_rw_derr	30.316m	13.254ms	10	10	100.00
		flash_ctrl_derr_detect	1.857m	235.804us	5	5	100.00
		flash_ctrl_integrity	31.414m	7.858ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.670s	316.641us	5	5	100.00
		flash_ctrl_ro_serr	5.533m	3.690ms	10	10	100.00
		flash_ctrl_rw_serr	26.776m	6.690ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.368m	2.919ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.282m	716.888us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.679m	5.200ms	20	20	100.00
		flash_ctrl_write_word_sweep	13.940s	22.838us	1	1	100.00
		flash_ctrl_read_word_sweep	13.410s	70.171us	1	1	100.00
		flash_ctrl_ro	5.136m	2.228ms	20	20	100.00
		flash_ctrl_rw	26.911m	9.679ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	35.750s	600.489us	4	5	80.00
V2	rma_write_process_error	flash_ctrl_rma_err	13.403m	39.747ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.598m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	16.190s	469.894us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.910s	37.144us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.710s	755.979us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.710s	755.979us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	38.090s	108.330us	5	5	100.00
		flash_ctrl_csr_rw	17.730s	712.424us	20	20	100.00
		flash_ctrl_csr_aliasing	56.770s	4.777ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.810s	170.279us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	38.090s	108.330us	5	5	100.00
		flash_ctrl_csr_rw	17.730s	712.424us	20	20	100.00
		flash_ctrl_csr_aliasing	56.770s	4.777ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.810s	170.279us	20	20	100.00
V2		TOTAL			993	1013	98.03
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	1.724m	175.799us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	1.724m	175.799us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	1.724m	175.799us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	1.724m	175.799us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	1.850m	677.644us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.334h	1.646ms	5	5	100.00
		flash_ctrl_tl_intg_err	14.934m	1.308ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	14.934m	1.308ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	14.934m	1.308ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.360s	117.861us	3	3	100.00
		flash_ctrl_wr_intg	14.950s	48.903us	1	3	33.33
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.666m	164.498us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.296m	97.753us	80	80	100.00
		flash_ctrl_disable	22.670s	39.321us	50	50	100.00
		flash_ctrl_sec_info_access	1.515m	11.244ms	50	50	100.00
		flash_ctrl_connect	16.410s	15.532us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.880s	39.348us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.730s	712.424us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.724m	175.799us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.730s	712.424us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.724m	175.799us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.730s	712.424us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	1.724m	175.799us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.670s	39.321us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.360s	117.861us	3	3	100.00
		flash_ctrl_access_after_disable	14.110s	13.722us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.670s	39.321us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	25.830s	1.009ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	26.911m	9.679ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	26.776m	6.690ms	10	10	100.00
		flash_ctrl_rw_derr	30.316m	13.254ms	10	10	100.00
		flash_ctrl_integrity	31.414m	7.858ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	32.507m	376.154ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.334h	1.646ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.334h	1.646ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.334h	1.646ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.334h	1.646ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	14.580s	23.081us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.130s	31.712us	3	5	60.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	13.940s	22.518us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.334h	1.646ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.334h	1.646ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.334h	1.646ms	5	5	100.00
V2S		TOTAL			140	144	97.22
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.160s	195.466us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1254	1278	98.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	47	85.45
V2S	12	12	10	83.33
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.52	95.50	94.31	98.95	92.52	97.34	98.30	98.72

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 7 failures:

Test flash_ctrl_fs_sup has 1 failures.

3.flash_ctrl_fs_sup.2397680367
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest/run.log

  UVM_ERROR @ 553220.3 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 553220.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_invalid_op has 6 failures.

7.flash_ctrl_invalid_op.1426855572
Line 3913, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 2105282.4 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 2105282.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.flash_ctrl_invalid_op.704304539
Line 1739, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 452038.5 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 452038.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (flash_phy_prim_monitor.sv:44) [monitor] timeout waiting for mon_start has 5 failures:

Test flash_ctrl_intr_rd_slow_flash has 4 failures.

6.flash_ctrl_intr_rd_slow_flash.758348424
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd_slow_flash/latest/run.log

  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.flash_ctrl_intr_rd_slow_flash.2570098577
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd_slow_flash/latest/run.log

  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test flash_ctrl_intr_wr_slow_flash has 1 failures.

9.flash_ctrl_intr_wr_slow_flash.3278980194
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(!$isunknown(mem_tl_o))' has 2 failures:

Test flash_ctrl_phy_host_grant_err has 2 failures.

2.flash_ctrl_phy_host_grant_err.4214459743
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o))'
  UVM_ERROR @ 92125.8 ns: (flash_ctrl.sv:1399) [ASSERT FAILED] MemRspPayLoad_A
  UVM_INFO @ 92125.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_phy_host_grant_err.4271991060
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o))'
  UVM_ERROR @ 8063.8 ns: (flash_ctrl.sv:1399) [ASSERT FAILED] MemRspPayLoad_A
  UVM_INFO @ 8063.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_env_cfg.sv:434) [cfg] Check failed bkdr_rd_data == scb_flash_model[addr] (* [*] vs * [*]) Memory model check failed in partition FlashPartInfo*, bank *, addr * (*) has 2 failures:

Test flash_ctrl_rand_ops has 2 failures.

11.flash_ctrl_rand_ops.1172951068
Line 269328, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rand_ops/latest/run.log

  UVM_ERROR @ 3033101.4 ns: (flash_ctrl_env_cfg.sv:434) [cfg] Check failed bkdr_rd_data == scb_flash_model[addr] (4294967295 [0xffffffff] vs 1935168028 [0x7358521c]) Memory model check failed in partition FlashPartInfo1, bank 1, addr 0x300 (768)
  UVM_INFO @ 3033101.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.flash_ctrl_rand_ops.1649801533
Line 275713, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rand_ops/latest/run.log

  UVM_ERROR @ 18144540.6 ns: (flash_ctrl_env_cfg.sv:434) [cfg] Check failed bkdr_rd_data == scb_flash_model[addr] (4294967295 [0xffffffff] vs 215538995 [0xcd8dd33]) Memory model check failed in partition FlashPartInfo2, bank 1, addr 0xc28 (3112)
  UVM_INFO @ 18144540.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:

Test flash_ctrl_rw_evict has 1 failures.

13.flash_ctrl_rw_evict.559133742
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 31031.1 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 31031.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_evict_all_en has 1 failures.

20.flash_ctrl_rw_evict_all_en.1782464283
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 21051.5 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 21051.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test flash_ctrl_full_mem_access has 1 failures.
  - 0.flash_ctrl_full_mem_access.2836184749
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:d6db4389-08ee-4b9c-8282-15a47f9dd3cf
```
UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert fatal_std_err did not trigger max_delay:* has 1 failures:
- Test flash_ctrl_wr_intg has 1 failures.
  - 1.flash_ctrl_wr_intg.50758278
    Line 263, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest/run.log
```
  UVM_ERROR @ 51192.2 ns: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_std_err did not trigger max_delay:2000
  UVM_INFO @ 51192.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:365) [wdata_page0_comp_bank1] *: obs:exp *_*_136af6d1_c72c2dc2:*_*_dc77febc_fc657f* mismatch!! has 1 failures:
- Test flash_ctrl_wr_intg has 1 failures.
  - 2.flash_ctrl_wr_intg.2427242434
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest/run.log
```
  UVM_ERROR @ 182854.7 ns: (flash_ctrl_otf_scoreboard.sv:365) [wdata_page0_comp_bank1]    0: obs:exp    88_0_136af6d1_c72c2dc2:97_8_dc77febc_fc657f22  mismatch!!
  UVM_INFO @ 182854.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_scoreboard.sv:819) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@151937) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict has 1 failures.

6.flash_ctrl_rw_evict.1388181790
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 15143.4 ns: (flash_ctrl_scoreboard.sv:819) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@151937) { a_addr: 'h72c84  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h70  a_opcode: 'h4  a_user: 'h248aa  d_param: 'h0  d_source: 'h70  d_data: 'h11c2224  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd3e  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 15143.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_scoreboard.sv:696) [scoreboard] Check failed exp_data_part[addr] == data (* [*] vs * [*]) read addr:* data: * has 1 failures:
- Test flash_ctrl_rand_ops has 1 failures.
  - 14.flash_ctrl_rand_ops.3654510512
    Line 310, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rand_ops/latest/run.log
```
  UVM_ERROR @ 47780.5 ns: (flash_ctrl_scoreboard.sv:696) [uvm_test_top.env.scoreboard] Check failed exp_data_part[addr] == data (3280716805 [0xc38bc405] vs 3292676108 [0xc442400c]) read addr:0x8070c data: 0xc442400c
  UVM_INFO @ 47780.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_scoreboard.sv:819) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@158593) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict has 1 failures.

17.flash_ctrl_rw_evict.2837706343
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 12843.6 ns: (flash_ctrl_scoreboard.sv:819) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@158593) { a_addr: 'he8144  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hce  a_opcode: 'h4  a_user: 'h254aa  d_param: 'h0  d_source: 'hce  d_data: 'h57d3dd42  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd38  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 12843.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---