FLASH_CTRL Simulation Results

Wednesday January 17 2024 20:02:30 UTC

GitHub Revision: 4d88b9516c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3635458896929517279689574864899235923834879224879080668186365324190153451241

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	2.871m	2.721ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	25.990s	17.755us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.310s	50.684us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.150s	176.384us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	2.092m	54.484ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.063m	4.970ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	18.880s	76.259us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.150s	176.384us	20	20	100.00
		flash_ctrl_csr_aliasing	1.063m	4.970ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.000s	15.089us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.730s	16.095us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.390s	22.795us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.103m	255.994us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	29.826m	124.253ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.888m	290.284ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.610s	46.428us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	45.379m	281.843ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.408m	9.321ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.505m	15.943ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	45.551m	307.039ms	4	5	80.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.139m	1.414ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	39.120s	2.406ms	40	40	100.00
		flash_ctrl_rw_evict_all_en	38.560s	130.822us	40	40	100.00
		flash_ctrl_re_evict	40.170s	674.304us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.545m	2.790ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.545m	2.790ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	17.430m	55.786ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.890s	487.871us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.547m	283.740us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.600m	8.856ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.312m	415.016us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	43.721m	852.199us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.820s	25.831us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.294m	4.749ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	3.337m	10.031ms	49	50	98.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.340s	35.632us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	23.532m	950.617us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.231m	32.351ms	50	50	100.00
		flash_ctrl_otp_reset	2.270m	347.726us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	29.826m	124.253ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.251m	1.938ms	40	40	100.00
		flash_ctrl_intr_wr	1.957m	10.212ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	4.226m	39.644ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	10.370m	202.382ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.617m	41.853ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.201m	970.885us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.550s	18.565us	5	5	100.00
		flash_ctrl_ro_derr	2.521m	692.281us	10	10	100.00
		flash_ctrl_rw_derr	13.030m	7.100ms	10	10	100.00
		flash_ctrl_derr_detect	1.753m	165.332us	5	5	100.00
		flash_ctrl_integrity	10.308m	3.341ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.000s	62.446us	5	5	100.00
		flash_ctrl_ro_serr	2.566m	8.057ms	10	10	100.00
		flash_ctrl_rw_serr	10.225m	3.797ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.398m	3.911ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.194m	598.423us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.629m	10.652ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.570s	126.405us	1	1	100.00
		flash_ctrl_read_word_sweep	13.120s	27.824us	1	1	100.00
		flash_ctrl_ro	1.971m	543.662us	20	20	100.00
		flash_ctrl_rw	11.796m	60.907ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	35.400s	1.114ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.200m	332.108ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.000m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.180s	105.368us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.640s	17.445us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.080s	232.550us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.080s	232.550us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.310s	50.684us	5	5	100.00
		flash_ctrl_csr_rw	17.150s	176.384us	20	20	100.00
		flash_ctrl_csr_aliasing	1.063m	4.970ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.700s	329.860us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.310s	50.684us	5	5	100.00
		flash_ctrl_csr_rw	17.150s	176.384us	20	20	100.00
		flash_ctrl_csr_aliasing	1.063m	4.970ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.700s	329.860us	20	20	100.00
V2		TOTAL			1011	1013	99.80
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.800s	14.492us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.800s	14.492us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.800s	14.492us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.800s	14.492us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.170s	11.824us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.341h	1.194ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.019m	1.268ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.019m	1.268ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.019m	1.268ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.800s	70.009us	3	3	100.00
		flash_ctrl_wr_intg	14.930s	247.303us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	2.871m	2.721ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.270m	347.726us	80	80	100.00
		flash_ctrl_disable	3.337m	10.031ms	49	50	98.00
		flash_ctrl_sec_info_access	1.589m	28.953ms	50	50	100.00
		flash_ctrl_connect	16.340s	35.632us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.930s	33.040us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.150s	176.384us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.800s	14.492us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.150s	176.384us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.800s	14.492us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.150s	176.384us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.800s	14.492us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	3.337m	10.031ms	49	50	98.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.800s	70.009us	3	3	100.00
		flash_ctrl_access_after_disable	13.450s	41.433us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	3.337m	10.031ms	49	50	98.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.890s	487.871us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.796m	60.907ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	10.225m	3.797ms	10	10	100.00
		flash_ctrl_rw_derr	13.030m	7.100ms	10	10	100.00
		flash_ctrl_integrity	10.308m	3.341ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	29.826m	124.253ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.341h	1.194ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.341h	1.194ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.341h	1.194ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.341h	1.194ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	21.850s	115.554us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.020s	14.806us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	13.880s	67.894us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.341h	1.194ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.341h	1.194ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.341h	1.194ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	46.940s	157.633us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1276	1278	99.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	53	96.36
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.71	95.86	94.17	98.95	92.52	98.46	98.30	98.68

Failure Buckets

• Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test flash_ctrl_full_mem_access has 1 failures.

    • 1.flash_ctrl_full_mem_access.80891988997009875888520235133027131625705194932871483784457581029473307104563
      Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest/run.log

        Job ID: smart:29513c52-6c6e-4b84-bd83-ea550d3a4b94
      

• UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.status.rd_empty (addr=*) == * has 1 failures:

  • Test flash_ctrl_disable has 1 failures.

    • 32.flash_ctrl_disable.43962727335073118831994094202986603408813340855365089937597160619254927625945
      Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_disable/latest/run.log

        UVM_FATAL @ 10031359.2 ns: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.status.rd_empty (addr=0xa62f5174) == 0x1
        UVM_INFO @ 10031359.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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