FLASH_CTRL Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: `5f48fbc0e7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.583m	70.468us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.390s	17.752us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.790s	47.387us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.610s	67.690us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.314m	5.894ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.104m	8.966ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.870s	130.438us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.610s	67.690us	20	20	100.00
		flash_ctrl_csr_aliasing	1.104m	8.966ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.630s	14.703us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.980s	56.086us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.470s	39.758us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.058m	178.203us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	30.797m	340.050ms	3	3	100.00
		flash_ctrl_hw_rma_reset	15.315m	160.192ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.730s	26.556us	18	20	90.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	41.879m	256.211ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.617m	16.012ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	39.950s	2.363ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	43.240m	162.762ms	2	5	40.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.223m	2.815ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	37.530s	103.970us	40	40	100.00
		flash_ctrl_rw_evict_all_en	36.830s	398.363us	40	40	100.00
		flash_ctrl_re_evict	40.570s	134.794us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.889m	15.393ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.889m	15.393ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	14.897m	11.648ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.270s	629.512us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	21.223m	874.192us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.984m	28.291ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.089m	10.452ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	42.967m	3.829ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.770s	45.960us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.292m	2.904ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	12.226m	10.006ms	44	50	88.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.180s	61.010us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	34.643m	2.001ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.258m	12.690ms	50	50	100.00
		flash_ctrl_otp_reset	2.256m	616.759us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	30.797m	340.050ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.179m	2.781ms	40	40	100.00
		flash_ctrl_intr_wr	1.977m	17.578ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.476m	87.609ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	20.810m	961.273ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.500m	1.960ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.266m	5.350ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.860s	18.711us	5	5	100.00
		flash_ctrl_ro_derr	2.913m	4.342ms	10	10	100.00
		flash_ctrl_rw_derr	11.146m	3.602ms	10	10	100.00
		flash_ctrl_derr_detect	1.765m	114.547us	5	5	100.00
		flash_ctrl_integrity	12.608m	55.816ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.080s	25.228us	5	5	100.00
		flash_ctrl_ro_serr	2.530m	6.317ms	10	10	100.00
		flash_ctrl_rw_serr	9.980m	21.454ms	9	10	90.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.275m	2.664ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.076m	512.313us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.998m	16.428ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.820s	134.596us	1	1	100.00
		flash_ctrl_read_word_sweep	14.300s	43.186us	1	1	100.00
		flash_ctrl_ro	1.895m	468.485us	20	20	100.00
		flash_ctrl_rw	10.734m	21.555ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	37.250s	301.360us	4	5	80.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.849m	154.369ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.662m	10.021ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.450s	120.439us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.070s	17.824us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.350s	58.432us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.350s	58.432us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.790s	47.387us	5	5	100.00
		flash_ctrl_csr_rw	17.610s	67.690us	20	20	100.00
		flash_ctrl_csr_aliasing	1.104m	8.966ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.070s	161.319us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.790s	47.387us	5	5	100.00
		flash_ctrl_csr_rw	17.610s	67.690us	20	20	100.00
		flash_ctrl_csr_aliasing	1.104m	8.966ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.070s	161.319us	20	20	100.00
V2		TOTAL			1000	1013	98.72
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.050s	57.446us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.050s	57.446us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.050s	57.446us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.050s	57.446us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	15.860s	15.088us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.355h	3.295ms	5	5	100.00
		flash_ctrl_tl_intg_err	14.978m	703.817us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	14.978m	703.817us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	14.978m	703.817us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.680s	454.803us	3	3	100.00
		flash_ctrl_wr_intg	14.880s	359.587us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.583m	70.468us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.256m	616.759us	80	80	100.00
		flash_ctrl_disable	12.226m	10.006ms	44	50	88.00
		flash_ctrl_sec_info_access	1.411m	2.639ms	50	50	100.00
		flash_ctrl_connect	16.180s	61.010us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.710s	36.209us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.610s	67.690us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.050s	57.446us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.610s	67.690us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.050s	57.446us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.610s	67.690us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.050s	57.446us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	12.226m	10.006ms	44	50	88.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.680s	454.803us	3	3	100.00
		flash_ctrl_access_after_disable	13.910s	20.520us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	12.226m	10.006ms	44	50	88.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.270s	629.512us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.734m	21.555ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	9.980m	21.454ms	9	10	90.00
		flash_ctrl_rw_derr	11.146m	3.602ms	10	10	100.00
		flash_ctrl_integrity	12.608m	55.816ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	30.797m	340.050ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.355h	3.295ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.355h	3.295ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.355h	3.295ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.355h	3.295ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	16.050s	85.159us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.400s	24.523us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	13.930s	49.612us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.355h	3.295ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.355h	3.295ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.355h	3.295ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.180s	59.360us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1265	1278	98.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	50	90.91
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.70	95.88	94.18	98.95	92.52	98.51	98.41	98.45

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 3 failures:
- Test flash_ctrl_full_mem_access has 3 failures.
  - 2.flash_ctrl_full_mem_access.35902792596856276900225104598153507728477298308100246277272214113586301858103
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:dd1568cf-7e86-4b5f-83a8-a0fc9a97b91f
```
  - 3.flash_ctrl_full_mem_access.68682414242501804927334964961876004640353087547924003955090981345648616318730
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:cd7a35b1-c587-46ca-96e1-5d6ccf37c613
```
  - ... and 1 more failures.

UVM_ERROR (cip_base_scoreboard.sv:455) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_core_reg_block, TL item: req: (cip_tl_seq_item@82720) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test flash_ctrl_disable has 2 failures.

0.flash_ctrl_disable.35521778003289272169024103604296920541827092897881480720886661061512628047623
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 9855.7 ns: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_core_reg_block, TL item: req: (cip_tl_seq_item@82720) { a_addr: 'h184d31b0  a_data: 'h8c99e072  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd9  a_opcode: 'h1  a_user: 'h253d8  d_param: 'h0  d_source: 'hd9  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 9855.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_disable.48395864291568525348150028284168087652981244993172794005426329351789620922411
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 7607.2 ns: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_core_reg_block, TL item: req: (cip_tl_seq_item@82720) { a_addr: 'h8b81dbb0  a_data: 'h3ab8240d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha7  a_opcode: 'h1  a_user: 'h276d0  d_param: 'h0  d_source: 'ha7  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 7607.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 2 failures:
- Test flash_ctrl_lcmgr_intg has 2 failures.
  - 0.flash_ctrl_lcmgr_intg.84009982807393065787569993808323353831477042996039576605580571447467373906005
    Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_lcmgr_intg/latest/run.log
```
  UVM_ERROR @ 98552.7 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
  UVM_INFO @ 98552.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.flash_ctrl_lcmgr_intg.90970970425607997625277443413900151486437928282888238710449477843479624396056
    Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_lcmgr_intg/latest/run.log
```
  UVM_ERROR @ 26556.3 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
  UVM_INFO @ 26556.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.status.rd_empty (addr=*) == * has 2 failures:
- Test flash_ctrl_disable has 2 failures.
  - 7.flash_ctrl_disable.73487433072810318520364616128515919133592281422873342143168962872572602393769
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 10005707.4 ns: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.status.rd_empty (addr=0xd9d41774) == 0x1
  UVM_INFO @ 10005707.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.flash_ctrl_disable.35591444221964177080322069230669448382310448256706620605981627620257442612101
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 10005593.0 ns: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.status.rd_empty (addr=0xe97c2574) == 0x1
  UVM_INFO @ 10005593.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:227) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_fs_sup has 1 failures.
  - 3.flash_ctrl_fs_sup.57544581262348354197641969307007026802550211342701843652711739859770360586112
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest/run.log
```
  UVM_ERROR @ 288256.9 ns: (cip_base_scoreboard.sv:227) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 288256.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rw_serr has 1 failures.
  - 6.flash_ctrl_rw_serr.3570880158002963914816115356035888005902768424797632994222282334937253230552
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest/run.log
```
  UVM_ERROR @ 2512852.4 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (4132938574859741270186 [0xe00c0b6896800d90aa] vs 1771755333424918663338 [0x600c0b6896800d90aa])
  UVM_INFO @ 2512852.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:455) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@79873) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_disable has 1 failures.

20.flash_ctrl_disable.85895179406883856031598233864062450338408436940285744281486293020718458985125
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 25155.8 ns: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@79873) { a_addr: 'h6b280  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'he1  a_opcode: 'h4  a_user: 'h2422a  d_param: 'h0  d_source: 'he1  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 25155.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:455) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@82642) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_disable has 1 failures.

28.flash_ctrl_disable.29393105257645308921935406053723156319819367875015615475099826093586184439570
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 7339.8 ns: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@82642) { a_addr: 'hab544  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h4  a_user: 'h251aa  d_param: 'h0  d_source: 'h3  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 7339.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---