FLASH_CTRL Simulation Results

Wednesday February 21 2024 20:04:41 UTC

GitHub Revision: `df66f8a42e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 105428938048998514387352931012238053576571450380985277214810281406530880002461

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.512m	9.700ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.460s	112.725us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	38.910s	83.046us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.990s	252.872us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	53.050s	1.265ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	58.540s	1.551ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.080s	91.603us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.990s	252.872us	20	20	100.00
		flash_ctrl_csr_aliasing	58.540s	1.551ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.440s	14.177us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.770s	19.082us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.160s	170.468us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.081m	481.115us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	30.998m	134.497ms	3	3	100.00
		flash_ctrl_hw_rma_reset	20.977m	630.468ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.180s	15.424us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	48.468m	301.021ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.278m	53.946ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	6.315m	4.581ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	46.724m	372.575ms	4	5	80.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.439m	3.674ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	35.370s	180.649us	40	40	100.00
		flash_ctrl_rw_evict_all_en	38.580s	122.079us	40	40	100.00
		flash_ctrl_re_evict	41.090s	648.743us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.238m	2.114ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.238m	2.114ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	15.682m	12.458ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.910s	2.078ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	21.290m	9.485ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.213m	112.679ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.435m	3.962ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	49.355m	458.728us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.670s	15.499us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.982m	1.839ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	37.157m	120.032ms	48	50	96.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.320s	14.711us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	29.679m	8.699ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.168m	11.866ms	50	50	100.00
		flash_ctrl_otp_reset	2.299m	78.257us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	30.998m	134.497ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.085m	4.535ms	40	40	100.00
		flash_ctrl_intr_wr	2.116m	20.311ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	4.311m	79.872ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	9.165m	180.682ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.585m	2.025ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.244m	3.218ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.700s	100.772us	5	5	100.00
		flash_ctrl_ro_derr	2.986m	1.522ms	10	10	100.00
		flash_ctrl_rw_derr	12.297m	4.633ms	10	10	100.00
		flash_ctrl_derr_detect	1.770m	305.183us	5	5	100.00
		flash_ctrl_integrity	10.465m	7.677ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.070s	82.536us	5	5	100.00
		flash_ctrl_ro_serr	2.205m	1.248ms	10	10	100.00
		flash_ctrl_rw_serr	13.467m	10.871ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.517m	898.259us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.341m	2.740ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.974m	10.875ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.500s	138.372us	1	1	100.00
		flash_ctrl_read_word_sweep	13.690s	17.064us	1	1	100.00
		flash_ctrl_ro	2.138m	572.097us	20	20	100.00
		flash_ctrl_rw	9.747m	7.795ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	37.410s	292.259us	4	5	80.00
V2	rma_write_process_error	flash_ctrl_rma_err	20.721m	443.103ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.049m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.650s	308.440us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.800s	60.056us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.060s	230.903us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.060s	230.903us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	38.910s	83.046us	5	5	100.00
		flash_ctrl_csr_rw	17.990s	252.872us	20	20	100.00
		flash_ctrl_csr_aliasing	58.540s	1.551ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.190s	257.315us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	38.910s	83.046us	5	5	100.00
		flash_ctrl_csr_rw	17.990s	252.872us	20	20	100.00
		flash_ctrl_csr_aliasing	58.540s	1.551ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.190s	257.315us	20	20	100.00
V2		TOTAL			1009	1013	99.61
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.300s	64.851us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.300s	64.851us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.300s	64.851us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.300s	64.851us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	15.970s	11.649us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.328h	10.529ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.111m	2.795ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.111m	2.795ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.111m	2.795ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.850s	110.268us	3	3	100.00
		flash_ctrl_wr_intg	14.620s	81.363us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.512m	9.700ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.299m	78.257us	80	80	100.00
		flash_ctrl_disable	37.157m	120.032ms	48	50	96.00
		flash_ctrl_sec_info_access	1.663m	26.528ms	50	50	100.00
		flash_ctrl_connect	16.320s	14.711us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.950s	22.469us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.990s	252.872us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.300s	64.851us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.990s	252.872us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.300s	64.851us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.990s	252.872us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.300s	64.851us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	37.157m	120.032ms	48	50	96.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.850s	110.268us	3	3	100.00
		flash_ctrl_access_after_disable	13.600s	14.158us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	37.157m	120.032ms	48	50	96.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.910s	2.078ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	9.747m	7.795ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	13.467m	10.871ms	10	10	100.00
		flash_ctrl_rw_derr	12.297m	4.633ms	10	10	100.00
		flash_ctrl_integrity	10.465m	7.677ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	30.998m	134.497ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.328h	10.529ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.328h	10.529ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.328h	10.529ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.328h	10.529ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	1.266m	794.857us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.330s	14.705us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	15.170s	30.723us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.328h	10.529ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.328h	10.529ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.328h	10.529ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.380s	123.563us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1274	1278	99.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	52	94.55
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.44	95.34	94.04	98.95	92.52	97.22	98.52	98.52

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test flash_ctrl_full_mem_access has 1 failures.
  - 4.flash_ctrl_full_mem_access.63270631615912283228321957462589623230317281548598316164791540576877165188808
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:3a27f94e-d752-4476-ada4-36934c3e44ba
```
UVM_ERROR (cip_base_scoreboard.sv:227) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_fs_sup has 1 failures.
  - 4.flash_ctrl_fs_sup.113391251746069334610067686072979291377043015381221484640289169978820175258529
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest/run.log
```
  UVM_ERROR @ 253275.3 ns: (cip_base_scoreboard.sv:227) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 253275.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.op_status.done (addr=*) == * has 1 failures:
- Test flash_ctrl_disable has 1 failures.
  - 36.flash_ctrl_disable.17724388940704570489623422746151881518920898681463413096908850697341756416188
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/36.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 120031804.1 ns: (csr_utils_pkg.sv:571) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.op_status.done (addr=0xe3a8d570) == 0x1
  UVM_INFO @ 120031804.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:452) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_core_reg_block, TL item: req: (cip_tl_seq_item@83716) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_disable has 1 failures.

43.flash_ctrl_disable.57188470221344327900629723915307676041389031451650034031499899406980298052174
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/43.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 33856.9 ns: (cip_base_scoreboard.sv:452) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_core_reg_block, TL item: req: (cip_tl_seq_item@83716) { a_addr: 'hc09a01b0  a_data: 'hf1a36860  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h97  a_opcode: 'h1  a_user: 'h26861  d_param: 'h0  d_source: 'h97  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 33856.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---