FLASH_CTRL Simulation Results

Sunday February 25 2024 20:02:21 UTC

GitHub Revision: 49a27e136c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17821327886248910358472250431024817182401150698618588470408418907520000067582

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.247m	704.903us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.260s	180.733us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.210s	164.101us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.840s	68.546us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.340m	8.773ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.253m	6.831ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.250s	1.346ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.840s	68.546us	20	20	100.00
		flash_ctrl_csr_aliasing	1.253m	6.831ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.720s	42.581us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.730s	60.303us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.720s	21.470us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.697m	167.752us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	30.461m	107.386ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.263m	160.197ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.810s	46.462us	19	20	95.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	42.244m	264.694ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.356m	3.490ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	19.880s	344.234us	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	46.832m	467.435ms	3	5	60.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.488m	1.435ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	35.280s	90.104us	40	40	100.00
		flash_ctrl_rw_evict_all_en	38.740s	304.356us	40	40	100.00
		flash_ctrl_re_evict	40.960s	2.288ms	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.788m	4.080ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.788m	4.080ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	16.959m	13.672ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.360s	551.839us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	19.723m	900.489us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	39.620m	3.816ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.787m	503.917us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	43.410m	961.516us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.030s	39.882us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.460m	15.462ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.780s	11.173us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.620s	17.002us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	27.631m	8.871ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.451m	6.093ms	50	50	100.00
		flash_ctrl_otp_reset	2.294m	76.931us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	30.461m	107.386ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.401m	7.825ms	40	40	100.00
		flash_ctrl_intr_wr	2.180m	27.110ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.739m	126.955ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	11.188m	347.430ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.595m	6.936ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.313m	10.282ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.630s	32.909us	5	5	100.00
		flash_ctrl_ro_derr	3.050m	2.647ms	10	10	100.00
		flash_ctrl_rw_derr	11.444m	56.968ms	10	10	100.00
		flash_ctrl_derr_detect	1.749m	321.022us	5	5	100.00
		flash_ctrl_integrity	11.592m	3.804ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.680s	25.796us	5	5	100.00
		flash_ctrl_ro_serr	2.420m	1.350ms	10	10	100.00
		flash_ctrl_rw_serr	10.794m	3.815ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.591m	846.391us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.349m	8.679ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.376m	3.301ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.570s	252.915us	1	1	100.00
		flash_ctrl_read_word_sweep	13.920s	42.556us	1	1	100.00
		flash_ctrl_ro	2.071m	6.452ms	20	20	100.00
		flash_ctrl_rw	10.264m	4.298ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	36.390s	1.121ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	13.474m	114.331ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.905m	10.018ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.670s	631.797us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.790s	21.878us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.850s	126.773us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.850s	126.773us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.210s	164.101us	5	5	100.00
		flash_ctrl_csr_rw	17.840s	68.546us	20	20	100.00
		flash_ctrl_csr_aliasing	1.253m	6.831ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.430s	510.238us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.210s	164.101us	5	5	100.00
		flash_ctrl_csr_rw	17.840s	68.546us	20	20	100.00
		flash_ctrl_csr_aliasing	1.253m	6.831ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.430s	510.238us	20	20	100.00
V2		TOTAL			1010	1013	99.70
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.100s	149.068us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.100s	149.068us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.100s	149.068us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.100s	149.068us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.070s	24.072us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.328h	6.183ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.079m	889.707us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.079m	889.707us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.079m	889.707us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.340s	215.613us	3	3	100.00
		flash_ctrl_wr_intg	15.080s	170.965us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.247m	704.903us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.294m	76.931us	80	80	100.00
		flash_ctrl_disable	22.780s	11.173us	50	50	100.00
		flash_ctrl_sec_info_access	1.381m	4.940ms	50	50	100.00
		flash_ctrl_connect	16.620s	17.002us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.060s	263.128us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.840s	68.546us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.100s	149.068us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.840s	68.546us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.100s	149.068us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.840s	68.546us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.100s	149.068us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.780s	11.173us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.340s	215.613us	3	3	100.00
		flash_ctrl_access_after_disable	13.940s	41.370us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.780s	11.173us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.360s	551.839us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.264m	4.298ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	10.794m	3.815ms	10	10	100.00
		flash_ctrl_rw_derr	11.444m	56.968ms	10	10	100.00
		flash_ctrl_integrity	11.592m	3.804ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	30.461m	107.386ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.328h	6.183ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.328h	6.183ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.328h	6.183ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.328h	6.183ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	44.450s	671.318us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.180s	64.813us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	15.430s	368.957us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.328h	6.183ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.328h	6.183ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.328h	6.183ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.560s	103.715us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1275	1278	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	53	96.36
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.71	95.89	94.20	98.95	92.52	98.49	98.41	98.55

Failure Buckets

• Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:

  • Test flash_ctrl_full_mem_access has 2 failures.

    • 1.flash_ctrl_full_mem_access.113870055525664533071691870993857970585792740908672737098670691813074990879656
      Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest/run.log

        Job ID: smart:ad5aa011-fa9b-40c1-bf5e-24a774218e94
      

    • 2.flash_ctrl_full_mem_access.23404782783825986445919047925652271440164982097166478436616779551907195572856
      Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest/run.log

        Job ID: smart:2a8c4db4-6825-4952-9bf1-0da8691566d6
      

• UVM_ERROR (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 1 failures:

  • Test flash_ctrl_lcmgr_intg has 1 failures.

    • 1.flash_ctrl_lcmgr_intg.87078257050039111820552403750057410443613077209132287558486213112060133631992
      Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_lcmgr_intg/latest/run.log

        UVM_ERROR @ 14019.0 ns: (csr_utils_pkg.sv:462) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
        UVM_INFO @ 14019.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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