FLASH_CTRL Simulation Results

Wednesday February 28 2024 23:53:28 UTC

GitHub Revision: 32ed2c4230

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10708067410766204292161266966839433462058030635847883045650346145926493105783

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.737m	40.652us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.390s	15.643us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.050s	25.895us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.920s	112.811us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.349m	14.585ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.064m	6.236ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.370s	347.698us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.920s	112.811us	20	20	100.00
		flash_ctrl_csr_aliasing	1.064m	6.236ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.890s	17.727us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.830s	51.557us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.850s	23.441us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.014m	68.750us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	37.793m	606.969ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.131m	320.285ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.900s	45.648us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	44.081m	267.641ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.382m	13.401ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.438m	3.969ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	59.633m	93.910ms	4	5	80.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.330m	5.537ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	37.920s	108.929us	40	40	100.00
		flash_ctrl_rw_evict_all_en	38.430s	114.971us	40	40	100.00
		flash_ctrl_re_evict	40.650s	289.770us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.756m	4.168ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.756m	4.168ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	21.035m	41.752ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.580s	776.364us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	25.154m	292.291us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.427m	62.036ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.090m	388.263us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	45.253m	1.618ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.460s	77.543us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.068m	4.861ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.560s	15.075us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.590s	41.299us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	24.028m	240.693us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.245m	3.034ms	50	50	100.00
		flash_ctrl_otp_reset	2.412m	46.189us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	37.793m	606.969ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.441m	1.225ms	40	40	100.00
		flash_ctrl_intr_wr	2.429m	70.169ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	4.874m	77.249ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	11.611m	187.292ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.543m	982.213us	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.306m	6.773ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.920s	55.107us	5	5	100.00
		flash_ctrl_ro_derr	2.727m	1.485ms	10	10	100.00
		flash_ctrl_rw_derr	12.923m	8.692ms	9	10	90.00
		flash_ctrl_derr_detect	1.823m	183.241us	5	5	100.00
		flash_ctrl_integrity	11.602m	20.120ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	24.430s	22.998us	5	5	100.00
		flash_ctrl_ro_serr	2.429m	568.311us	10	10	100.00
		flash_ctrl_rw_serr	11.469m	11.935ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.163m	2.821ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.255m	688.842us	5	5	100.00
V2	scramble	flash_ctrl_wo	4.119m	11.349ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.500s	119.039us	1	1	100.00
		flash_ctrl_read_word_sweep	14.380s	254.901us	1	1	100.00
		flash_ctrl_ro	1.953m	850.719us	20	20	100.00
		flash_ctrl_rw	11.072m	40.287ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	40.190s	3.768ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	19.399m	365.706ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.115m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	16.190s	409.013us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	15.440s	48.278us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.560s	216.212us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.560s	216.212us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.050s	25.895us	5	5	100.00
		flash_ctrl_csr_rw	17.920s	112.811us	20	20	100.00
		flash_ctrl_csr_aliasing	1.064m	6.236ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.260s	422.511us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.050s	25.895us	5	5	100.00
		flash_ctrl_csr_rw	17.920s	112.811us	20	20	100.00
		flash_ctrl_csr_aliasing	1.064m	6.236ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.260s	422.511us	20	20	100.00
V2		TOTAL			1011	1013	99.80
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.160s	19.968us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.160s	19.968us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.160s	19.968us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.160s	19.968us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.620s	29.802us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.333h	5.321ms	5	5	100.00
		flash_ctrl_tl_intg_err	16.494m	2.072ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	16.494m	2.072ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	16.494m	2.072ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.410s	216.264us	3	3	100.00
		flash_ctrl_wr_intg	14.690s	167.304us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.737m	40.652us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.412m	46.189us	80	80	100.00
		flash_ctrl_disable	23.560s	15.075us	50	50	100.00
		flash_ctrl_sec_info_access	1.513m	22.472ms	50	50	100.00
		flash_ctrl_connect	16.590s	41.299us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.250s	45.085us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.920s	112.811us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.160s	19.968us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.920s	112.811us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.160s	19.968us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.920s	112.811us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.160s	19.968us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.560s	15.075us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.410s	216.264us	3	3	100.00
		flash_ctrl_access_after_disable	13.890s	34.526us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.560s	15.075us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.580s	776.364us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.072m	40.287ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.469m	11.935ms	10	10	100.00
		flash_ctrl_rw_derr	12.923m	8.692ms	9	10	90.00
		flash_ctrl_integrity	11.602m	20.120ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	37.793m	606.969ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.333h	5.321ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.333h	5.321ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.333h	5.321ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.333h	5.321ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	1.263m	835.356us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.110s	17.996us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.200s	25.002us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.333h	5.321ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.333h	5.321ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.333h	5.321ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	47.220s	190.664us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1276	1278	99.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	53	96.36
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.34	95.35	94.08	98.95	91.84	97.25	98.30	98.61

Failure Buckets

• Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test flash_ctrl_full_mem_access has 1 failures.

    • 1.flash_ctrl_full_mem_access.32053964184139187000815468920442893727900777540790329127331800813661545310412
      Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest/run.log

        Job ID: smart:55f47828-cba7-4e8f-9b3f-4153e3aa954c
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:289) m_otf_scb [process_read] unexpected double bit error * has 1 failures:

  • Test flash_ctrl_rw_derr has 1 failures.

    • 8.flash_ctrl_rw_derr.38484216696453156816846596276959834493670061817945129591411477260211340292889
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest/run.log

        UVM_ERROR @ 7294310.9 ns: (flash_ctrl_otf_scoreboard.sv:289) uvm_test_top.env.m_otf_scb [process_read] unexpected double bit error 0x00040000
        UVM_INFO @ 7294310.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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