FLASH_CTRL Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: e0c4026501

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.593m	48.097us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.690s	47.627us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.450s	88.132us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.810s	118.397us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.336m	2.347ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	55.870s	1.824ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.730s	402.024us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.810s	118.397us	20	20	100.00
		flash_ctrl_csr_aliasing	55.870s	1.824ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.580s	50.210us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.590s	35.080us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.740s	21.153us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.077m	66.699us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	41.125m	731.817ms	3	3	100.00
		flash_ctrl_hw_rma_reset	15.345m	160.198ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.900s	60.684us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	49.587m	302.285ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.466m	15.214ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	40.810s	684.751us	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	47.511m	389.618ms	4	5	80.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.575m	2.600ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	34.880s	209.690us	40	40	100.00
		flash_ctrl_rw_evict_all_en	38.050s	437.569us	40	40	100.00
		flash_ctrl_re_evict	40.530s	291.061us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.721m	6.218ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.721m	6.218ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	18.140m	72.431ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.960s	1.132ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	27.968m	1.343ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	38.145m	14.586ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	20.439m	2.529ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	44.636m	805.736us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.920s	32.409us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	2.910m	1.992ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.740s	22.476us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.360s	15.924us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	22.502m	2.988ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.258m	10.509ms	50	50	100.00
		flash_ctrl_otp_reset	2.331m	79.007us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	41.125m	731.817ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.495m	9.373ms	40	40	100.00
		flash_ctrl_intr_wr	2.655m	57.837ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.201m	65.831ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	9.321m	214.318ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.676m	13.810ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.410m	9.203ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.620s	19.396us	5	5	100.00
		flash_ctrl_ro_derr	2.758m	1.479ms	10	10	100.00
		flash_ctrl_rw_derr	12.267m	12.376ms	10	10	100.00
		flash_ctrl_derr_detect	1.821m	129.823us	4	5	80.00
		flash_ctrl_integrity	10.262m	17.192ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.250s	25.609us	5	5	100.00
		flash_ctrl_ro_serr	2.429m	2.888ms	10	10	100.00
		flash_ctrl_rw_serr	11.345m	19.894ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.369m	1.744ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.647m	985.979us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.737m	16.768ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.330s	62.289us	1	1	100.00
		flash_ctrl_read_word_sweep	13.930s	143.260us	1	1	100.00
		flash_ctrl_ro	2.011m	4.093ms	20	20	100.00
		flash_ctrl_rw	11.764m	41.897ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	40.130s	4.450ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	14.182m	568.505ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.414m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.900s	374.632us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.970s	80.163us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.160s	183.220us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.160s	183.220us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.450s	88.132us	5	5	100.00
		flash_ctrl_csr_rw	17.810s	118.397us	20	20	100.00
		flash_ctrl_csr_aliasing	55.870s	1.824ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.730s	155.446us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.450s	88.132us	5	5	100.00
		flash_ctrl_csr_rw	17.810s	118.397us	20	20	100.00
		flash_ctrl_csr_aliasing	55.870s	1.824ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.730s	155.446us	20	20	100.00
V2		TOTAL			1011	1013	99.80
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.980s	40.340us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.980s	40.340us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.980s	40.340us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.980s	40.340us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.130s	14.219us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.343h	5.380ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.051m	1.345ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.051m	1.345ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.051m	1.345ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.970s	113.936us	3	3	100.00
		flash_ctrl_wr_intg	14.800s	82.795us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.593m	48.097us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.331m	79.007us	80	80	100.00
		flash_ctrl_disable	22.740s	22.476us	50	50	100.00
		flash_ctrl_sec_info_access	1.447m	12.915ms	50	50	100.00
		flash_ctrl_connect	16.360s	15.924us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.980s	47.600us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.810s	118.397us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.980s	40.340us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.810s	118.397us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.980s	40.340us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.810s	118.397us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.980s	40.340us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.740s	22.476us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.970s	113.936us	3	3	100.00
		flash_ctrl_access_after_disable	13.770s	14.223us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.740s	22.476us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.960s	1.132ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.764m	41.897ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.345m	19.894ms	10	10	100.00
		flash_ctrl_rw_derr	12.267m	12.376ms	10	10	100.00
		flash_ctrl_integrity	10.262m	17.192ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	41.125m	731.817ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.343h	5.380ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.343h	5.380ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.343h	5.380ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.343h	5.380ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	1.277m	834.747us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.190s	15.271us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.460s	16.072us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.343h	5.380ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.343h	5.380ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.343h	5.380ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.460s	634.929us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1276	1278	99.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	53	96.36
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.30	95.34	93.99	98.95	91.84	97.18	98.30	98.52

Failure Buckets

• Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test flash_ctrl_full_mem_access has 1 failures.

    • 2.flash_ctrl_full_mem_access.69417571997396971627434432981577135880881363464414942501201531004587614891486
      Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest/run.log

        Job ID: smart:b2dfffbb-63c6-4574-9abc-340f1b892a3a
      

• UVM_ERROR (cip_base_scoreboard.sv:227) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:

  • Test flash_ctrl_derr_detect has 1 failures.

    • 4.flash_ctrl_derr_detect.76778755608092165669375832418691808372213003236779782514242672328836358515782
      Line 284, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log

        UVM_ERROR @ 36071.5 ns: (cip_base_scoreboard.sv:227) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 36071.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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