FLASH_CTRL Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: 0cdf265eaa

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.284m	65.659us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.800s	55.450us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.980s	139.297us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.360s	69.578us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.437m	3.217ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	51.830s	2.940ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	21.080s	175.376us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.360s	69.578us	20	20	100.00
		flash_ctrl_csr_aliasing	51.830s	2.940ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.550s	15.341us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.680s	56.987us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.920s	82.816us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.038m	146.572us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	28.271m	169.013ms	3	3	100.00
		flash_ctrl_hw_rma_reset	25.859m	760.408ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.140s	44.840us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	35.716m	384.645ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.158m	5.402ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	5.204m	5.928ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	50.318m	313.024ms	4	5	80.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.477m	1.465ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	37.210s	108.009us	39	40	97.50
		flash_ctrl_rw_evict_all_en	39.830s	283.688us	40	40	100.00
		flash_ctrl_re_evict	40.670s	246.710us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.639m	4.995ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.639m	4.995ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	17.016m	13.682ms	19	20	95.00
V2	fetch_code	flash_ctrl_fetch_code	34.160s	4.270ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	22.189m	6.673ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	39.496m	26.043ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.608m	14.591ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	56.968m	984.460us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.150s	15.285us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.197m	1.097ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.240s	127.800us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.480s	21.160us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	11.253m	549.229us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.514m	2.984ms	50	50	100.00
		flash_ctrl_otp_reset	2.343m	139.479us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	28.271m	169.013ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.518m	10.682ms	40	40	100.00
		flash_ctrl_intr_wr	2.017m	33.173ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	6.243m	35.856ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	8.476m	174.892ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.553m	4.854ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.258m	1.133ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.970s	61.107us	5	5	100.00
		flash_ctrl_ro_derr	2.820m	1.871ms	10	10	100.00
		flash_ctrl_rw_derr	11.598m	13.687ms	10	10	100.00
		flash_ctrl_derr_detect	1.788m	354.310us	5	5	100.00
		flash_ctrl_integrity	10.547m	20.977ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.070s	40.227us	5	5	100.00
		flash_ctrl_ro_serr	2.716m	649.562us	10	10	100.00
		flash_ctrl_rw_serr	9.988m	3.953ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.393m	1.566ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.435m	3.263ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.805m	29.624ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.840s	63.951us	1	1	100.00
		flash_ctrl_read_word_sweep	14.640s	23.915us	1	1	100.00
		flash_ctrl_ro	2.190m	2.265ms	20	20	100.00
		flash_ctrl_rw	10.338m	3.996ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	44.490s	4.045ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	14.584m	39.762ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.168m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.770s	50.790us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.790s	141.956us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.870s	206.692us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.870s	206.692us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.980s	139.297us	5	5	100.00
		flash_ctrl_csr_rw	17.360s	69.578us	20	20	100.00
		flash_ctrl_csr_aliasing	51.830s	2.940ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.870s	839.689us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.980s	139.297us	5	5	100.00
		flash_ctrl_csr_rw	17.360s	69.578us	20	20	100.00
		flash_ctrl_csr_aliasing	51.830s	2.940ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.870s	839.689us	20	20	100.00
V2		TOTAL			1010	1013	99.70
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.200s	15.247us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.200s	15.247us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.200s	15.247us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.200s	15.247us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.030s	165.308us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.358h	1.437ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.482m	6.589ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.482m	6.589ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.482m	6.589ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.520s	385.982us	3	3	100.00
		flash_ctrl_wr_intg	15.010s	166.939us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.284m	65.659us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.343m	139.479us	80	80	100.00
		flash_ctrl_disable	23.240s	127.800us	50	50	100.00
		flash_ctrl_sec_info_access	1.419m	5.140ms	50	50	100.00
		flash_ctrl_connect	16.480s	21.160us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.180s	26.067us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.360s	69.578us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.200s	15.247us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.360s	69.578us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.200s	15.247us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.360s	69.578us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.200s	15.247us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.240s	127.800us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.520s	385.982us	3	3	100.00
		flash_ctrl_access_after_disable	14.140s	22.877us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.240s	127.800us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	34.160s	4.270ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.338m	3.996ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	9.988m	3.953ms	10	10	100.00
		flash_ctrl_rw_derr	11.598m	13.687ms	10	10	100.00
		flash_ctrl_integrity	10.547m	20.977ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	28.271m	169.013ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.358h	1.437ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.358h	1.437ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.358h	1.437ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.358h	1.437ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	1.410m	914.323us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.260s	17.047us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.700s	58.981us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.358h	1.437ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.358h	1.437ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.358h	1.437ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	49.270s	103.520us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1275	1278	99.77

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	52	94.55
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.58	95.77	94.17	98.95	92.52	98.28	98.30	98.09

Failure Buckets

• Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test flash_ctrl_full_mem_access has 1 failures.

    • 1.flash_ctrl_full_mem_access.58987332124264549596558978908695960464326425899257418220025216731068590016128
      Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest/run.log

        Job ID: smart:01538a8f-1527-4305-a895-d70526e120bf
      

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_err did not trigger max_delay:* has 1 failures:

  • Test flash_ctrl_mp_regions has 1 failures.

    • 16.flash_ctrl_mp_regions.6767025674722674135412030174042717755395140264641605303493017589491732052592
      Line 3199, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_mp_regions/latest/run.log

        UVM_ERROR @ 1172518.6 ns: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_err did not trigger max_delay:2000
        UVM_INFO @ 1172518.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:

  • Test flash_ctrl_rw_evict has 1 failures.

    • 32.flash_ctrl_rw_evict.9553102694748216898151062403725427385030337316119247825423312077152782543591
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 8088.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 8088.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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