Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	0.00	0.00	0.00		0.00	0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	0.00	0.00		0.00
u_enc	0.00	0.00
u_plain_enc	0.00	0.00
u_state_regs	0.00	0.00				0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	0.00	0.00		0.00
u_enc	0.00	0.00
u_plain_enc	0.00	0.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		93	0	0.00
CONT_ASSIGN	111	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	0	0.00
ALWAYS	130	3	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	143	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	147	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
ALWAYS	151	6	0	0.00
ALWAYS	164	3	0	0.00
ALWAYS	174	50	0	0.00
ALWAYS	299	10	0	0.00
CONT_ASSIGN	314	1	0	0.00
ALWAYS	323	4	0	0.00
CONT_ASSIGN	331	1	0	0.00
CONT_ASSIGN	352	1	0	0.00
CONT_ASSIGN	355	1	0	0.00
CONT_ASSIGN	365	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
ALWAYS	369	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	0	1
122	0	1
126	0	1
130	0	1
131	0	1
133	0	1
138	0	1
143	0	1
144	0	1
147	0	1
148	0	1
151	0	1
152	0	1
153	0	1
155	0	1
156	0	1
158	0	1
			==> MISSING_ELSE
164	0	3
174	0	1
176	0	1
177	0	1
178	0	1
179	0	1
180	0	1
181	0	1
182	0	1
183	0	1
184	0	1
186	0	1
189	0	1
193	0	1
194	0	1
195	0	1
196	0	1
197	0	1
			==> MISSING_ELSE
203	0	1
204	0	1
205	0	1
			==> MISSING_ELSE
210	0	1
211	0	1
213	0	1
215	0	1
216	0	1
218	0	1
219	0	1
220	0	1
			==> MISSING_ELSE
226	0	1
227	0	1
230	0	1
231	0	1
			==> MISSING_ELSE
236	0	1
237	0	1
241	0	1
243	0	1
244		unreachable
			==> MISSING_ELSE
249	0	1
251	0	1
252	0	1
			==> MISSING_ELSE
257	0	1
262	0	1
263	0	1
269	0	1
270	0	1
272	0	1
273	0	1
278	0	1
279	0	1
280	0	1
			==> MISSING_ELSE
285	0	1
299	0	1
300	0	1
301	0	1
302	0	1
303	0	1
304	0	1
305		unreachable
306		unreachable
307	0	1
308	0	1
309	0	1
310	0	1
			==> MISSING_ELSE
314	0	1
323	0	1
324	0	1
325	0	1
326	0	1
			==> MISSING_ELSE
331	0	1
352	0	1
355	0	1
365	0	1
366	0	1
369	0	1
370	0	1
372	0	1

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	63	0	0.00
Logical	63	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	0	0.00	(Not included in score)
Transitions	15	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Not Covered
StCalcMask	237	Not Covered
StCalcPlainEcc	215	Not Covered
StDisabled	193	Not Covered
StIdle	273	Not Covered
StPackData	197	Not Covered
StPostPack	218	Not Covered
StPrePack	195	Not Covered
StReqFlash	237	Not Covered
StScrambleData	244	Not Covered
StWaitFlash	270	Not Covered

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Not Covered
StCalcMask->StScrambleData	244	Not Covered
StCalcPlainEcc->StCalcMask	237	Not Covered
StCalcPlainEcc->StReqFlash	237	Not Covered
StIdle->StDisabled	193	Not Covered
StIdle->StPackData	197	Not Covered
StIdle->StPrePack	195	Not Covered
StPackData->StCalcPlainEcc	215	Not Covered
StPackData->StPostPack	218	Not Covered
StPostPack->StCalcPlainEcc	231	Not Covered
StPrePack->StPackData	205	Not Covered
StReqFlash->StIdle	273	Not Covered
StReqFlash->StWaitFlash	270	Not Covered
StScrambleData->StCalcEcc	252	Not Covered
StWaitFlash->StIdle	280	Not Covered

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		53	0	0.00
TERNARY	111	2	0	0.00
TERNARY	148	2	0	0.00
TERNARY	355	2	0	0.00
TERNARY	366	3	0	0.00
IF	130	2	0	0.00
IF	151	4	0	0.00
IF	164	2	0	0.00
CASE	186	26	0	0.00
IF	299	5	0	0.00
IF	323	3	0	0.00
IF	369	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Not Covered
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Not Covered
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Unreachable
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Not Covered
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Not Covered
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Not Covered
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Not Covered
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Not Covered
0	1	-	-	-	Not Covered
0	0	1	-	-	Unreachable
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		93	0	0.00
CONT_ASSIGN	111	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	0	0.00
ALWAYS	130	3	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	143	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	147	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
ALWAYS	151	6	0	0.00
ALWAYS	164	3	0	0.00
ALWAYS	174	50	0	0.00
ALWAYS	299	10	0	0.00
CONT_ASSIGN	314	1	0	0.00
ALWAYS	323	4	0	0.00
CONT_ASSIGN	331	1	0	0.00
CONT_ASSIGN	352	1	0	0.00
CONT_ASSIGN	355	1	0	0.00
CONT_ASSIGN	365	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
ALWAYS	369	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	0	1
122	0	1
126	0	1
130	0	1
131	0	1
133	0	1
138	0	1
143	0	1
144	0	1
147	0	1
148	0	1
151	0	1
152	0	1
153	0	1
155	0	1
156	0	1
158	0	1
			==> MISSING_ELSE
164	0	3
174	0	1
176	0	1
177	0	1
178	0	1
179	0	1
180	0	1
181	0	1
182	0	1
183	0	1
184	0	1
186	0	1
189	0	1
193	0	1
194	0	1
195	0	1
196	0	1
197	0	1
			==> MISSING_ELSE
203	0	1
204	0	1
205	0	1
			==> MISSING_ELSE
210	0	1
211	0	1
213	0	1
215	0	1
216	0	1
218	0	1
219	0	1
220	0	1
			==> MISSING_ELSE
226	0	1
227	0	1
230	0	1
231	0	1
			==> MISSING_ELSE
236	0	1
237	0	1
241	0	1
243	0	1
244		unreachable
			==> MISSING_ELSE
249	0	1
251	0	1
252	0	1
			==> MISSING_ELSE
257	0	1
262	0	1
263	0	1
269	0	1
270	0	1
272	0	1
273	0	1
278	0	1
279	0	1
280	0	1
			==> MISSING_ELSE
285	0	1
299	0	1
300	0	1
301	0	1
302	0	1
303	0	1
304	0	1
305		unreachable
306		unreachable
307	0	1
308	0	1
309	0	1
310	0	1
			==> MISSING_ELSE
314	0	1
323	0	1
324	0	1
325	0	1
326	0	1
			==> MISSING_ELSE
331	0	1
352	0	1
355	0	1
365	0	1
366	0	1
369	0	1
370	0	1
372	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	63	0	0.00
Logical	63	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	0	0.00	(Not included in score)
Transitions	15	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Not Covered
StCalcMask	237	Not Covered
StCalcPlainEcc	215	Not Covered
StDisabled	193	Not Covered
StIdle	273	Not Covered
StPackData	197	Not Covered
StPostPack	218	Not Covered
StPrePack	195	Not Covered
StReqFlash	237	Not Covered
StScrambleData	244	Not Covered
StWaitFlash	270	Not Covered

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Not Covered
StCalcMask->StScrambleData	244	Not Covered
StCalcPlainEcc->StCalcMask	237	Not Covered
StCalcPlainEcc->StReqFlash	237	Not Covered
StIdle->StDisabled	193	Not Covered
StIdle->StPackData	197	Not Covered
StIdle->StPrePack	195	Not Covered
StPackData->StCalcPlainEcc	215	Not Covered
StPackData->StPostPack	218	Not Covered
StPostPack->StCalcPlainEcc	231	Not Covered
StPrePack->StPackData	205	Not Covered
StReqFlash->StIdle	273	Not Covered
StReqFlash->StWaitFlash	270	Not Covered
StScrambleData->StCalcEcc	252	Not Covered
StWaitFlash->StIdle	280	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		53	0	0.00
TERNARY	111	2	0	0.00
TERNARY	148	2	0	0.00
TERNARY	355	2	0	0.00
TERNARY	366	3	0	0.00
IF	130	2	0	0.00
IF	151	4	0	0.00
IF	164	2	0	0.00
CASE	186	26	0	0.00
IF	299	5	0	0.00
IF	323	3	0	0.00
IF	369	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Not Covered
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Not Covered
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Unreachable
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Not Covered
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Not Covered
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Not Covered
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Not Covered
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Not Covered
0	1	-	-	-	Not Covered
0	0	1	-	-	Unreachable
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		93	0	0.00
CONT_ASSIGN	111	1	0	0.00
CONT_ASSIGN	122	1	0	0.00
CONT_ASSIGN	126	1	0	0.00
ALWAYS	130	3	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	143	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	147	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
ALWAYS	151	6	0	0.00
ALWAYS	164	3	0	0.00
ALWAYS	174	50	0	0.00
ALWAYS	299	10	0	0.00
CONT_ASSIGN	314	1	0	0.00
ALWAYS	323	4	0	0.00
CONT_ASSIGN	331	1	0	0.00
CONT_ASSIGN	352	1	0	0.00
CONT_ASSIGN	355	1	0	0.00
CONT_ASSIGN	365	1	0	0.00
CONT_ASSIGN	366	1	0	0.00
ALWAYS	369	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
111	0	1
122	0	1
126	0	1
130	0	1
131	0	1
133	0	1
138	0	1
143	0	1
144	0	1
147	0	1
148	0	1
151	0	1
152	0	1
153	0	1
155	0	1
156	0	1
158	0	1
			==> MISSING_ELSE
164	0	3
174	0	1
176	0	1
177	0	1
178	0	1
179	0	1
180	0	1
181	0	1
182	0	1
183	0	1
184	0	1
186	0	1
189	0	1
193	0	1
194	0	1
195	0	1
196	0	1
197	0	1
			==> MISSING_ELSE
203	0	1
204	0	1
205	0	1
			==> MISSING_ELSE
210	0	1
211	0	1
213	0	1
215	0	1
216	0	1
218	0	1
219	0	1
220	0	1
			==> MISSING_ELSE
226	0	1
227	0	1
230	0	1
231	0	1
			==> MISSING_ELSE
236	0	1
237	0	1
241	0	1
243	0	1
244		unreachable
			==> MISSING_ELSE
249	0	1
251	0	1
252	0	1
			==> MISSING_ELSE
257	0	1
262	0	1
263	0	1
269	0	1
270	0	1
272	0	1
273	0	1
278	0	1
279	0	1
280	0	1
			==> MISSING_ELSE
285	0	1
299	0	1
300	0	1
301	0	1
302	0	1
303	0	1
304	0	1
305		unreachable
306		unreachable
307	0	1
308	0	1
309	0	1
310	0	1
			==> MISSING_ELSE
314	0	1
323	0	1
324	0	1
325	0	1
326	0	1
			==> MISSING_ELSE
331	0	1
352	0	1
355	0	1
365	0	1
366	0	1
369	0	1
370	0	1
372	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	63	0	0.00
Logical	63	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	0	0.00	(Not included in score)
Transitions	15	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Not Covered
StCalcMask	237	Not Covered
StCalcPlainEcc	215	Not Covered
StDisabled	193	Not Covered
StIdle	273	Not Covered
StPackData	197	Not Covered
StPostPack	218	Not Covered
StPrePack	195	Not Covered
StReqFlash	237	Not Covered
StScrambleData	244	Not Covered
StWaitFlash	270	Not Covered

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Not Covered
StCalcMask->StScrambleData	244	Not Covered
StCalcPlainEcc->StCalcMask	237	Not Covered
StCalcPlainEcc->StReqFlash	237	Not Covered
StIdle->StDisabled	193	Not Covered
StIdle->StPackData	197	Not Covered
StIdle->StPrePack	195	Not Covered
StPackData->StCalcPlainEcc	215	Not Covered
StPackData->StPostPack	218	Not Covered
StPostPack->StCalcPlainEcc	231	Not Covered
StPrePack->StPackData	205	Not Covered
StReqFlash->StIdle	273	Not Covered
StReqFlash->StWaitFlash	270	Not Covered
StScrambleData->StCalcEcc	252	Not Covered
StWaitFlash->StIdle	280	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		53	0	0.00
TERNARY	111	2	0	0.00
TERNARY	148	2	0	0.00
TERNARY	355	2	0	0.00
TERNARY	366	3	0	0.00
IF	130	2	0	0.00
IF	151	4	0	0.00
IF	164	2	0	0.00
CASE	186	26	0	0.00
IF	299	5	0	0.00
IF	323	3	0	0.00
IF	369	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_prog.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	111	((data_sel == Actual)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	148	((idx > '0)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	355	(ecc_i) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	366	(txn_done) ? 
-2-:	366	(done) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	130	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	151	if ((!rst_ni))
-2-:	153	if ((pack_valid && (idx == MaxIdx)))
-3-:	156	if (pack_valid)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	164	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	186	case (state_q)
-2-:	189	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	194	if ((req_i && (|sel_i)))
-4-:	196	if (req_i)
-5-:	204	if ((idx == align_next))
-6-:	213	if ((req_i && (idx == MaxIdx)))
-7-:	216	if ((req_i && last_i))
-8-:	219	if (req_i)
-9-:	230	if ((idx == MaxIdx))
-10-:	237	(scramble_i) ? 
-11-:	243	if (calc_ack_i)
-12-:	251	if (scramble_ack_i)
-13-:	269	if (last_i)
-14-:	270	(ack) ? 
-15-:	273	(ack) ? 
-16-:	278	if (done)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Not Covered
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Not Covered
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Not Covered
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Unreachable
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Not Covered
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Not Covered
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Not Covered
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Not Covered
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	299	if ((!rst_ni))
-2-:	302	if ((req_o && ack))
-3-:	304	if ((calc_req_o && calc_ack_i))
-4-:	307	if ((scramble_req_o && scramble_ack_i))
-5-:	309	if (pack_valid)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Not Covered
0	1	-	-	-	Not Covered
0	0	1	-	-	Unreachable
0	0	0	1	-	Not Covered
0	0	0	0	1	Not Covered
0	0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	323	if ((!rst_ni))
-2-:	325	if (plain_ecc_en)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	369	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered