Unified Coverage Report :: Module :: flash_phy_core

Module : flash_phy_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core	0.00	0.00	0.00		0.00	0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	0.00	0.00	0.00	0.00	0.00	0.00
u_disable_buf	0.00	0.00
u_erase	0.00	0.00	0.00		0.00	0.00
u_host_arb	0.00	0.00	0.00			0.00
u_host_outstanding_cnt	0.00			0.00
u_rd	0.00	0.00	0.00	0.00		0.00
u_scramble	0.00	0.00	0.00	0.00		0.00
u_state_regs	0.00	0.00				0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_prog_data.u_prog	0.00	0.00	0.00	0.00	0.00	0.00
u_disable_buf	0.00	0.00
u_erase	0.00	0.00	0.00		0.00	0.00
u_host_arb	0.00	0.00	0.00			0.00
u_host_outstanding_cnt	0.00			0.00
u_rd	0.00	0.00	0.00	0.00		0.00
u_scramble	0.00	0.00	0.00	0.00		0.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
TOTAL		79	0	0.00
ALWAYS	154	6	0	0.00
ALWAYS	167	3	0	0.00
CONT_ASSIGN	199	1	0	0.00
CONT_ASSIGN	203	1	0	0.00
ALWAYS	206	4	0	0.00
ALWAYS	218	6	0	0.00
ALWAYS	232	6	0	0.00
CONT_ASSIGN	280	1	0	0.00
CONT_ASSIGN	283	1	0	0.00
CONT_ASSIGN	284	1	0	0.00
CONT_ASSIGN	285	1	0	0.00
CONT_ASSIGN	290	1	0	0.00
CONT_ASSIGN	320	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
ALWAYS	328	29	0	0.00
CONT_ASSIGN	391	1	0	0.00
CONT_ASSIGN	395	1	0	0.00
CONT_ASSIGN	396	1	0	0.00
CONT_ASSIGN	397	1	0	0.00
CONT_ASSIGN	398	1	0	0.00
CONT_ASSIGN	399	1	0	0.00
CONT_ASSIGN	400	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	418	1	0	0.00
CONT_ASSIGN	431	1	0	0.00
CONT_ASSIGN	551	1	0	0.00
CONT_ASSIGN	579	1	0	0.00
CONT_ASSIGN	586	1	0	0.00
CONT_ASSIGN	603	1	0	0.00
CONT_ASSIGN	604	1	0	0.00
CONT_ASSIGN	605	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	0	1
155	0	1
156	0	1
157	0	1
158	0	1
159	0	1
			==> MISSING_ELSE
167	0	3
199	0	1
203	0	1
206	0	1
207	0	1
208	0	1
209	0	1
			==> MISSING_ELSE
218	0	1
219	0	1
220	0	1
221	0	1
222	0	1
223	0	1
			==> MISSING_ELSE
232	0	1
233	0	1
234	0	1
235	0	1
236	0	1
237	0	1
			==> MISSING_ELSE
280	0	1
283	0	1
284	0	1
285	0	1
290	0	1
320	0	1
324	0	1
328	0	1
329	0	1
330	0	1
331	0	1
332	0	1
334	0	1
336	0	1
337	0	1
338	0	1
339	0	1
340	0	1
341	0	1
342	0	1
343	0	1
344	0	1
			==> MISSING_ELSE
350	0	1
351	0	1
352	0	1
			==> MISSING_ELSE
359	0	1
360	0	1
361	0	1
362	0	1
			==> MISSING_ELSE
368	0	1
369	0	1
370	0	1
371	0	1
372	0	1
			==> MISSING_ELSE
377	0	1
378	0	1
391	0	1
395	0	1
396	0	1
397	0	1
398	0	1
399	0	1
400	0	1
401	0	1
418	0	1
431	0	1
551	0	1
579	0	1
586	0	1
603	0	1
604	0	1
605	0	1

---

Cond Coverage for Module : flash_phy_core

	Total	Covered	Percent
Conditions	106	0	0.00
Logical	106	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       284
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       285
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       320
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       320
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       324
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       339
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       341
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       391
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       391
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       391
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       391
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       395
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       396
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       397
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       398
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       399
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       400
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       401
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       401
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       431
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       431
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       431
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       434
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       434
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       434
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       557
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       557
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       557
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       579
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Module : flash_phy_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	7	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	344	Not Covered
StCtrlProg	342	Not Covered
StCtrlRead	340	Not Covered
StDisable	338	Not Covered
StIdle	352	Not Covered

transitions	Line No.	Covered	Tests
StCtrl->StIdle	372	Not Covered
StCtrlProg->StIdle	362	Not Covered
StCtrlRead->StIdle	352	Not Covered
StIdle->StCtrl	344	Not Covered
StIdle->StCtrlProg	342	Not Covered
StIdle->StCtrlRead	340	Not Covered
StIdle->StDisable	338	Not Covered

---

Branch Coverage for Module : flash_phy_core

	Line No.	Total	Covered	Percent
Branches		46	0	0.00
TERNARY	320	2	0	0.00
TERNARY	395	2	0	0.00
TERNARY	396	2	0	0.00
TERNARY	397	2	0	0.00
TERNARY	398	2	0	0.00
TERNARY	551	2	0	0.00
TERNARY	434	2	0	0.00
TERNARY	557	2	0	0.00
IF	154	4	0	0.00
IF	167	2	0	0.00
IF	206	3	0	0.00
IF	218	4	0	0.00
IF	232	4	0	0.00
CASE	334	13	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	398	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	434	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	557	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	334	case (state_q)
-2-:	337	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	339	if ((ctrl_gnt && rd_i))
-4-:	341	if ((ctrl_gnt && prog_i))
-5-:	343	if (ctrl_gnt)
-6-:	350	if (rd_stage_data_valid)
-7-:	360	if (prog_ack)
-8-:	370	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Not Covered
StIdle	0	1	-	-	-	-	-	Not Covered
StIdle	0	0	1	-	-	-	-	Not Covered
StIdle	0	0	0	1	-	-	-	Not Covered
StIdle	0	0	0	0	-	-	-	Not Covered
StCtrlRead	-	-	-	-	1	-	-	Not Covered
StCtrlRead	-	-	-	-	0	-	-	Not Covered
StCtrlProg	-	-	-	-	-	1	-	Not Covered
StCtrlProg	-	-	-	-	-	0	-	Not Covered
StCtrl	-	-	-	-	-	-	1	Not Covered
StCtrl	-	-	-	-	-	-	0	Not Covered
StDisable	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
TOTAL		79	0	0.00
ALWAYS	154	6	0	0.00
ALWAYS	167	3	0	0.00
CONT_ASSIGN	199	1	0	0.00
CONT_ASSIGN	203	1	0	0.00
ALWAYS	206	4	0	0.00
ALWAYS	218	6	0	0.00
ALWAYS	232	6	0	0.00
CONT_ASSIGN	280	1	0	0.00
CONT_ASSIGN	283	1	0	0.00
CONT_ASSIGN	284	1	0	0.00
CONT_ASSIGN	285	1	0	0.00
CONT_ASSIGN	290	1	0	0.00
CONT_ASSIGN	320	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
ALWAYS	328	29	0	0.00
CONT_ASSIGN	391	1	0	0.00
CONT_ASSIGN	395	1	0	0.00
CONT_ASSIGN	396	1	0	0.00
CONT_ASSIGN	397	1	0	0.00
CONT_ASSIGN	398	1	0	0.00
CONT_ASSIGN	399	1	0	0.00
CONT_ASSIGN	400	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	418	1	0	0.00
CONT_ASSIGN	431	1	0	0.00
CONT_ASSIGN	551	1	0	0.00
CONT_ASSIGN	579	1	0	0.00
CONT_ASSIGN	586	1	0	0.00
CONT_ASSIGN	603	1	0	0.00
CONT_ASSIGN	604	1	0	0.00
CONT_ASSIGN	605	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	0	1
155	0	1
156	0	1
157	0	1
158	0	1
159	0	1
			==> MISSING_ELSE
167	0	3
199	0	1
203	0	1
206	0	1
207	0	1
208	0	1
209	0	1
			==> MISSING_ELSE
218	0	1
219	0	1
220	0	1
221	0	1
222	0	1
223	0	1
			==> MISSING_ELSE
232	0	1
233	0	1
234	0	1
235	0	1
236	0	1
237	0	1
			==> MISSING_ELSE
280	0	1
283	0	1
284	0	1
285	0	1
290	0	1
320	0	1
324	0	1
328	0	1
329	0	1
330	0	1
331	0	1
332	0	1
334	0	1
336	0	1
337	0	1
338	0	1
339	0	1
340	0	1
341	0	1
342	0	1
343	0	1
344	0	1
			==> MISSING_ELSE
350	0	1
351	0	1
352	0	1
			==> MISSING_ELSE
359	0	1
360	0	1
361	0	1
362	0	1
			==> MISSING_ELSE
368	0	1
369	0	1
370	0	1
371	0	1
372	0	1
			==> MISSING_ELSE
377	0	1
378	0	1
391	0	1
395	0	1
396	0	1
397	0	1
398	0	1
399	0	1
400	0	1
401	0	1
418	0	1
431	0	1
551	0	1
579	0	1
586	0	1
603	0	1
604	0	1
605	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Total	Covered	Percent
Conditions	106	0	0.00
Logical	106	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       284
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       285
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       320
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       320
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       324
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       339
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       341
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       391
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       391
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       391
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       391
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       395
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       396
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       397
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       398
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       399
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       400
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       401
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       401
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       431
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       431
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       431
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       434
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       434
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       434
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       557
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       557
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       557
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       579
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	7	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	344	Not Covered
StCtrlProg	342	Not Covered
StCtrlRead	340	Not Covered
StDisable	338	Not Covered
StIdle	352	Not Covered

transitions	Line No.	Covered	Tests
StCtrl->StIdle	372	Not Covered
StCtrlProg->StIdle	362	Not Covered
StCtrlRead->StIdle	352	Not Covered
StIdle->StCtrl	344	Not Covered
StIdle->StCtrlProg	342	Not Covered
StIdle->StCtrlRead	340	Not Covered
StIdle->StDisable	338	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core

	Line No.	Total	Covered	Percent
Branches		46	0	0.00
TERNARY	320	2	0	0.00
TERNARY	395	2	0	0.00
TERNARY	396	2	0	0.00
TERNARY	397	2	0	0.00
TERNARY	398	2	0	0.00
TERNARY	551	2	0	0.00
TERNARY	434	2	0	0.00
TERNARY	557	2	0	0.00
IF	154	4	0	0.00
IF	167	2	0	0.00
IF	206	3	0	0.00
IF	218	4	0	0.00
IF	232	4	0	0.00
CASE	334	13	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	398	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	434	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	557	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	334	case (state_q)
-2-:	337	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	339	if ((ctrl_gnt && rd_i))
-4-:	341	if ((ctrl_gnt && prog_i))
-5-:	343	if (ctrl_gnt)
-6-:	350	if (rd_stage_data_valid)
-7-:	360	if (prog_ack)
-8-:	370	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Not Covered
StIdle	0	1	-	-	-	-	-	Not Covered
StIdle	0	0	1	-	-	-	-	Not Covered
StIdle	0	0	0	1	-	-	-	Not Covered
StIdle	0	0	0	0	-	-	-	Not Covered
StCtrlRead	-	-	-	-	1	-	-	Not Covered
StCtrlRead	-	-	-	-	0	-	-	Not Covered
StCtrlProg	-	-	-	-	-	1	-	Not Covered
StCtrlProg	-	-	-	-	-	0	-	Not Covered
StCtrl	-	-	-	-	-	-	1	Not Covered
StCtrl	-	-	-	-	-	-	0	Not Covered
StDisable	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
TOTAL		79	0	0.00
ALWAYS	154	6	0	0.00
ALWAYS	167	3	0	0.00
CONT_ASSIGN	199	1	0	0.00
CONT_ASSIGN	203	1	0	0.00
ALWAYS	206	4	0	0.00
ALWAYS	218	6	0	0.00
ALWAYS	232	6	0	0.00
CONT_ASSIGN	280	1	0	0.00
CONT_ASSIGN	283	1	0	0.00
CONT_ASSIGN	284	1	0	0.00
CONT_ASSIGN	285	1	0	0.00
CONT_ASSIGN	290	1	0	0.00
CONT_ASSIGN	320	1	0	0.00
CONT_ASSIGN	324	1	0	0.00
ALWAYS	328	29	0	0.00
CONT_ASSIGN	391	1	0	0.00
CONT_ASSIGN	395	1	0	0.00
CONT_ASSIGN	396	1	0	0.00
CONT_ASSIGN	397	1	0	0.00
CONT_ASSIGN	398	1	0	0.00
CONT_ASSIGN	399	1	0	0.00
CONT_ASSIGN	400	1	0	0.00
CONT_ASSIGN	401	1	0	0.00
CONT_ASSIGN	418	1	0	0.00
CONT_ASSIGN	431	1	0	0.00
CONT_ASSIGN	551	1	0	0.00
CONT_ASSIGN	579	1	0	0.00
CONT_ASSIGN	586	1	0	0.00
CONT_ASSIGN	603	1	0	0.00
CONT_ASSIGN	604	1	0	0.00
CONT_ASSIGN	605	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
154	0	1
155	0	1
156	0	1
157	0	1
158	0	1
159	0	1
			==> MISSING_ELSE
167	0	3
199	0	1
203	0	1
206	0	1
207	0	1
208	0	1
209	0	1
			==> MISSING_ELSE
218	0	1
219	0	1
220	0	1
221	0	1
222	0	1
223	0	1
			==> MISSING_ELSE
232	0	1
233	0	1
234	0	1
235	0	1
236	0	1
237	0	1
			==> MISSING_ELSE
280	0	1
283	0	1
284	0	1
285	0	1
290	0	1
320	0	1
324	0	1
328	0	1
329	0	1
330	0	1
331	0	1
332	0	1
334	0	1
336	0	1
337	0	1
338	0	1
339	0	1
340	0	1
341	0	1
342	0	1
343	0	1
344	0	1
			==> MISSING_ELSE
350	0	1
351	0	1
352	0	1
			==> MISSING_ELSE
359	0	1
360	0	1
361	0	1
362	0	1
			==> MISSING_ELSE
368	0	1
369	0	1
370	0	1
371	0	1
372	0	1
			==> MISSING_ELSE
377	0	1
378	0	1
391	0	1
395	0	1
396	0	1
397	0	1
398	0	1
399	0	1
400	0	1
401	0	1
418	0	1
431	0	1
551	0	1
579	0	1
586	0	1
603	0	1
604	0	1
605	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Total	Covered	Percent
Conditions	106	0	0.00
Logical	106	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       199
 EXPRESSION (host_gnt && (muxed_part != FlashPartData))
             ----1---    --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       199
 SUB-EXPRESSION (muxed_part != FlashPartData)
                --------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       203
 EXPRESSION (((|host_outstanding)) & ((!ctrl_fsm_idle)))
             ----------1----------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       208
 EXPRESSION (host_gnt_err_event | host_outstanding_err_event)
             ---------1--------   -------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       220
 EXPRESSION (host_outstanding == '0)
            ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       234
 EXPRESSION ((host_outstanding == '0) && ctrl_fsm_idle)
             ------------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       234
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       245
 EXPRESSION (host_gnt && ((!host_req_done_o)) && (host_outstanding <= flash_phy_pkg::RspOrderDepth))
             ----1---    ----------2---------    -------------------------3------------------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       245
 EXPRESSION (((!host_gnt)) && host_req_done_o && ((|host_outstanding)))
             ------1------    -------2-------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       284
 EXPRESSION (host_req & host_req_rdy_o)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       285
 EXPRESSION (((|host_outstanding)) & rd_stage_data_valid)
             ----------1----------   ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       320
 EXPRESSION ((phy_req & host_req) ? rd_stage_rdy : rd_stage_idle)
             ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       320
 SUB-EXPRESSION (phy_req & host_req)
                 ---1---   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       324
 EXPRESSION (req_i & host_gnt)
             --1--   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       339
 EXPRESSION (ctrl_gnt && rd_i)
             ----1---    --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       341
 EXPRESSION (ctrl_gnt && prog_i)
             ----1---    ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       391
 EXPRESSION ((ctrl_fsm_idle & ctrl_rsp_vld) | ((host_outstanding == '0) & host_req_done_o))
             ---------------1--------------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       391
 SUB-EXPRESSION (ctrl_fsm_idle & ctrl_rsp_vld)
                 ------1------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       391
 SUB-EXPRESSION ((host_outstanding == '0) & host_req_done_o)
                 ------------1-----------   -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       391
 SUB-EXPRESSION (host_outstanding == '0)
                ------------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       395
 EXPRESSION (host_sel ? host_addr_i : addr_i)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       396
 EXPRESSION (host_sel ? FlashPartData : part_i)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       397
 EXPRESSION (host_sel ? host_scramble_en_i : scramble_en_i)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       398
 EXPRESSION (host_sel ? host_ecc_en_i : ecc_en_i)
             ----1---

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       399
 EXPRESSION (ctrl_rsp_vld & rd_i)
             ------1-----   --2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       400
 EXPRESSION (ctrl_rsp_vld & prog_i)
             ------1-----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       401
 EXPRESSION (ctrl_rsp_vld & (pg_erase_i | bk_erase_i))
             ------1-----   ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       401
 SUB-EXPRESSION (pg_erase_i | bk_erase_i)
                 -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       431
 EXPRESSION ((host_gnt_rd_err & (host_outstanding == 1'b1)) | host_outstanding_rd_err)
             -----------------------1----------------------   -----------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       431
 SUB-EXPRESSION (host_gnt_rd_err & (host_outstanding == 1'b1))
                 -------1-------   -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       431
 SUB-EXPRESSION (host_outstanding == 1'b1)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       434
 EXPRESSION (phy_req & (rd_i | host_req))
             ---1---   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       434
 SUB-EXPRESSION (rd_i | host_req)
                 --1-   ----2---

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       434
 EXPRESSION (arb_host_gnt_err ? ({flash_phy_pkg::FullDataWidth {1'b1}}) : flash_rdata)
             --------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       551
 EXPRESSION (prog_calc_req ? muxed_addr[(flash_phy_pkg::BusBankAddrW - 1):flash_phy_pkg::LsbAddrBit] : rd_calc_addr)
             ------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       557
 EXPRESSION (prog_calc_req | rd_calc_req)
             ------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       557
 EXPRESSION (prog_op_req | rd_op_req)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       557
 EXPRESSION (prog_op_req ? ScrambleOp : DeScrambleOp)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       579
 EXPRESSION (fsm_err | prog_fsm_err)
             ---1---   ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

Summary for FSM :: state_q

	Total	Covered	Percent
States	5	0	0.00	(Not included in score)
Transitions	7	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCtrl	344	Not Covered
StCtrlProg	342	Not Covered
StCtrlRead	340	Not Covered
StDisable	338	Not Covered
StIdle	352	Not Covered

transitions	Line No.	Covered	Tests
StCtrl->StIdle	372	Not Covered
StCtrlProg->StIdle	362	Not Covered
StCtrlRead->StIdle	352	Not Covered
StIdle->StCtrl	344	Not Covered
StIdle->StCtrlProg	342	Not Covered
StIdle->StCtrlRead	340	Not Covered
StIdle->StDisable	338	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core

	Line No.	Total	Covered	Percent
Branches		46	0	0.00
TERNARY	320	2	0	0.00
TERNARY	395	2	0	0.00
TERNARY	396	2	0	0.00
TERNARY	397	2	0	0.00
TERNARY	398	2	0	0.00
TERNARY	551	2	0	0.00
TERNARY	434	2	0	0.00
TERNARY	557	2	0	0.00
IF	154	4	0	0.00
IF	167	2	0	0.00
IF	206	3	0	0.00
IF	218	4	0	0.00
IF	232	4	0	0.00
CASE	334	13	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	320	((phy_req & host_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	395	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	396	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	397	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	398	(host_sel) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	551	(prog_calc_req) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	434	(arb_host_gnt_err) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	557	(prog_op_req) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	154	if ((!rst_ni))
-2-:	156	if (ctrl_rsp_vld)
-3-:	158	if (inc_arb_cnt)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	167	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	206	if ((!rst_ni))
-2-:	208	if ((host_gnt_err_event | host_outstanding_err_event))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	218	if ((!rst_ni))
-2-:	220	if ((host_outstanding == '0))
-3-:	222	if (host_gnt_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	232	if ((!rst_ni))
-2-:	234	if (((host_outstanding == '0) && ctrl_fsm_idle))
-3-:	236	if (host_outstanding_err_event)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	334	case (state_q)
-2-:	337	if (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[FsmDisableIdx]))
-3-:	339	if ((ctrl_gnt && rd_i))
-4-:	341	if ((ctrl_gnt && prog_i))
-5-:	343	if (ctrl_gnt)
-6-:	350	if (rd_stage_data_valid)
-7-:	360	if (prog_ack)
-8-:	370	if (erase_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
StIdle	1	-	-	-	-	-	-	Not Covered
StIdle	0	1	-	-	-	-	-	Not Covered
StIdle	0	0	1	-	-	-	-	Not Covered
StIdle	0	0	0	1	-	-	-	Not Covered
StIdle	0	0	0	0	-	-	-	Not Covered
StCtrlRead	-	-	-	-	1	-	-	Not Covered
StCtrlRead	-	-	-	-	0	-	-	Not Covered
StCtrlProg	-	-	-	-	-	1	-	Not Covered
StCtrlProg	-	-	-	-	-	0	-	Not Covered
StCtrl	-	-	-	-	-	-	1	Not Covered
StCtrl	-	-	-	-	-	-	0	Not Covered
StDisable	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	Not Covered