Unified Coverage Report :: Module :: flash_ctrl_lcmgr

Module : flash_ctrl_lcmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_flash_hw_if	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_flash_hw_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
8.45	0.00	0.00	42.26	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_addr_cnt	0.00			0.00
u_addr_sync_reqack	0.00	0.00	0.00			0.00
u_bus_intg	0.00	0.00
u_data_intg_chk	44.38	0.00		88.75
u_data_sync_reqack	0.00	0.00	0.00			0.00
u_page_cnt	0.00			0.00
u_prim_flop_err_sts	0.00	0.00				0.00
u_rma_state_regs	0.00	0.00				0.00
u_seed_cnt	0.00			0.00
u_state_regs	0.00	0.00				0.00
u_sync_flash_init	0.00	0.00				0.00
u_sync_rma_req	0.00	0.00				0.00
u_wipe_idx_cnt	0.00			0.00
u_word_cnt	0.00			0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_lcmgr

	Line No.	Total	Covered	Percent
TOTAL		242	0	0.00
CONT_ASSIGN	149	1	0	0.00
ALWAYS	152	3	0	0.00
CONT_ASSIGN	170	1	0	0.00
CONT_ASSIGN	171	1	0	0.00
ALWAYS	174	7	0	0.00
CONT_ASSIGN	185	1	0	0.00
ALWAYS	227	5	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	247	1	0	0.00
ALWAYS	251	3	0	0.00
CONT_ASSIGN	261	1	0	0.00
CONT_ASSIGN	262	1	0	0.00
ALWAYS	264	6	0	0.00
CONT_ASSIGN	278	1	0	0.00
CONT_ASSIGN	279	1	0	0.00
CONT_ASSIGN	280	1	0	0.00
ALWAYS	359	9	0	0.00
CONT_ASSIGN	380	1	0	0.00
ALWAYS	386	85	0	0.00
CONT_ASSIGN	607	1	0	0.00
ALWAYS	613	3	0	0.00
ALWAYS	673	7	0	0.00
ALWAYS	688	10	0	0.00
ALWAYS	705	2	0	0.00
CONT_ASSIGN	714	1	0	0.00
CONT_ASSIGN	715	1	0	0.00
CONT_ASSIGN	737	1	0	0.00
CONT_ASSIGN	741	1	0	0.00
CONT_ASSIGN	742	1	0	0.00
CONT_ASSIGN	754	1	0	0.00
ALWAYS	761	66	0	0.00
CONT_ASSIGN	891	1	0	0.00
CONT_ASSIGN	892	1	0	0.00
CONT_ASSIGN	893	1	0	0.00
CONT_ASSIGN	894	0	0
CONT_ASSIGN	895	0	0
CONT_ASSIGN	896	1	0	0.00
CONT_ASSIGN	897	1	0	0.00
CONT_ASSIGN	898	1	0	0.00
CONT_ASSIGN	900	1	0	0.00
CONT_ASSIGN	902	1	0	0.00
CONT_ASSIGN	905	1	0	0.00
CONT_ASSIGN	906	1	0	0.00
CONT_ASSIGN	908	1	0	0.00
CONT_ASSIGN	909	1	0	0.00
CONT_ASSIGN	911	1	0	0.00
CONT_ASSIGN	914	1	0	0.00
CONT_ASSIGN	918	1	0	0.00
CONT_ASSIGN	921	1	0	0.00
ALWAYS	932	0	0
CONT_ASSIGN	939	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
149	0	1
152	0	3
170	0	1
171	0	1
174	0	1
175	0	1
176	0	1
177	0	1
179	0	1
180	0	1
181	0	1
185	0	1
227	0	1
228	0	1
229	0	1
231	0	1
232	0	1
243	0	1
247	0	1
251	0	1
252	0	1
254	0	1
261	0	1
262	0	1
264	0	1
265	0	1
266	0	1
268	0	1
270	0	1
271	0	1
			==> MISSING_ELSE
278	0	1
279	0	1
280	0	1
359	0	1
360	0	1
361	0	1
363	0	1
364	0	1
365	0	1
			==> MISSING_ELSE
368	0	1
369	0	1
370	0	1
			==> MISSING_ELSE
380	0	1
386	0	1
389	0	1
390	0	1
391	0	1
392	0	1
395	0	1
396	0	1
397	0	1
398	0	1
399	0	1
402	0	1
404	0	1
405	0	1
406	0	1
409	0	1
411	0	1
412	0	1
415	0	1
416	0	1
419	0	1
420	0	1
423	0	1
425	0	1
427	0	1
433	0	1
434	0	1
435	0	1
436	0	1
			==> MISSING_ELSE
441	0	1
442	0	1
443	0	1
444	0	1
445	0	1
446	0	1
			==> MISSING_ELSE
451	0	1
452	0	1
453	0	1
454	0	1
455	0	1
457	0	1
			==> MISSING_ELSE
464	0	1
467	0	1
468	0	1
469	0	1
472	0	1
473	0	1
474	0	1
475	0	1
476	0	1
477	0	1
478	0	1
			==> MISSING_ELSE
483	0	1
484	0	1
485	0	1
487	0	1
488	0	1
489	0	1
491	0	1
497	0	1
498	0	1
499	0	1
			==> MISSING_ELSE
505	0	1
506	0	1
507	0	1
			==> MISSING_ELSE
512	0	1
513	0	1
514	0	1
516	0	1
520	0	1
521	0	1
522	0	1
			==> MISSING_ELSE
531	0	1
532	0	1
533	0	1
534	0	1
536	0	1
543	0	1
544	0	1
545	0	1
549	0	1
550	0	1
551	0	1
552	0	1
569	0	1
572	0	1
			==> MISSING_ELSE
607	0	1
613	0	3
673	0	1
674	0	1
675	0	1
676	0	1
678	0	1
679	0	1
680	0	1
688	0	1
689	0	1
690	0	1
691	0	1
692	0	1
693	0	1
694	0	1
			==> MISSING_ELSE
696	0	1
697	0	1
698	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
705	0	1
706	0	1
			==> MISSING_ELSE
714	0	1
715	0	1
737	0	1
741	0	1
742	0	1
754	0	1
761	0	1
762	0	1
763	0	1
764	0	1
765	0	1
766	0	1
767	0	1
768	0	1
769	0	1
770	0	1
771	0	1
772	0	1
773	0	1
774	0	1
775	0	1
777	0	1
784	0	1
785	0	1
786	0	1
787	0	1
788	0	1
			==> MISSING_ELSE
793	0	1
794	0	1
795	0	1
796	0	1
798	0	1
799	0	1
800	0	1
805	0	1
806	0	1
807	0	1
808	0	1
809	0	1
			==> MISSING_ELSE
814	0	1
815	0	1
819	0	1
820	0	1
821	0	1
822	0	1
824	0	1
825	0	1
826	0	1
831	0	1
832	0	1
833	0	1
835	0	1
836	0	1
			==> MISSING_ELSE
841	0	1
842	0	1
844	0	1
845	0	1
846	0	1
847	0	1
			==> MISSING_ELSE
852	0	1
853	0	1
854	0	1
856	0	1
857	0	1
858	0	1
859	0	1
			==> MISSING_ELSE
862	0	1
863	0	1
			==> MISSING_ELSE
868	0	1
872	0	1
873	0	1
874	0	1
891	0	1
892	0	1
893	0	1
894		unreachable
895		unreachable
896	0	1
897	0	1
898	0	1
900	0	1
902	0	1
905	0	1
906	0	1
908	0	1
909	0	1
911	0	1
914	0	1
918	0	1
921	0	1
932		unreachable
933		unreachable
			==> MISSING_ELSE
939	0	1

---

Cond Coverage for Module : flash_ctrl_lcmgr

	Total	Covered	Percent
Conditions	96	0	0.00
Logical	96	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       170
 EXPRESSION (phase == PhaseSeed)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       171
 EXPRESSION (phase == PhaseRma)
            ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       185
 EXPRESSION (seed_err_q | seed_err_d)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       231
 EXPRESSION (addr_cnt_err_q | addr_cnt_err_d)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       232
 EXPRESSION (seed_cnt_err_q | seed_cnt_err_d)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       247
 EXPRESSION (data_invalid_q | (rvalid_i & ((~data_intg_ok))))
             -------1------   ---------------2--------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       247
 SUB-EXPRESSION (rvalid_i & ((~data_intg_ok)))
                 ----1---   --------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       266
 EXPRESSION (seed_phase && validate_q && rvalid_i)
             -----1----    -----2----    ----3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       270
 EXPRESSION (seed_phase && rvalid_i)
             -----1----    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       363
 EXPRESSION (addr_key_req_d && addr_key_ack_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       368
 EXPRESSION (data_key_req_d && data_key_ack_q)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       457
 EXPRESSION (provision_en_i ? StReadSeeds : StWait)
             -------1------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       473
 EXPRESSION (seed_cnt_q == flash_ctrl_pkg::NumSeeds)
            --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       516
 EXPRESSION ((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done)
             --------------------------1-------------------------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       516
 SUB-EXPRESSION (rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0])
                --------------------------1-------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       678
 EXPRESSION (page_err_q | page_err_d)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       679
 EXPRESSION (word_err_q | word_err_d)
             -----1----   -----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       680
 EXPRESSION (rma_idx_err_q | rma_idx_err_d)
             ------1------   ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       693
 EXPRESSION (wvalid_o && wready_i)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       697
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       705
 EXPRESSION (prog_cnt_en && wvalid_o && wready_i)
             -----1-----    ----2---    ----3---

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       835
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i)
             -----------------------1----------------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       835
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       856
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i)
             -----------------------1----------------------    ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       856
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       862
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Unreachable
1	1	Not Covered

 LINE       863
 EXPRESSION (prog_data[beat_cnt] != rdata_i[(flash_ctrl_pkg::BusWidth - 1):0])
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       892
 EXPRESSION (seed_phase ? start : rma_start)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       893
 EXPRESSION (seed_phase ? op : rma_op)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       896
 EXPRESSION (seed_phase ? part_sel : rma_part_sel)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       897
 EXPRESSION (seed_phase ? info_sel : rma_info_sel)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       898
 EXPRESSION (seed_phase ? num_words : rma_num_words)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       900
 EXPRESSION (seed_phase ? ({addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}) : ({rma_addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}))
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       906
 EXPRESSION (seed_phase | rma_phase)
             -----1----   ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       914
 EXPRESSION (page_err_q | word_err_q | fsm_err | state_err | rma_idx_err_q | addr_cnt_err_q | seed_cnt_err_q)
             -----1----   -----2----   ---3---   ----4----   ------5------   -------6------   -------7------

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
0	0	0	0	0	0	0	Not Covered
0	0	0	0	0	0	1	Not Covered
0	0	0	0	0	1	0	Not Covered
0	0	0	0	1	0	0	Not Covered
0	0	0	1	0	0	0	Not Covered
0	0	1	0	0	0	0	Not Covered
0	1	0	0	0	0	0	Not Covered
1	0	0	0	0	0	0	Not Covered

---

FSM Coverage for Module : flash_ctrl_lcmgr

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	0	0.00	(Not included in score)
Transitions	25	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StDisabled	545	Not Covered
StEntropyReseed	499	Not Covered
StIdle	432	Not Covered
StInvalid	520	Not Covered
StReadEval	478	Not Covered
StReadSeeds	457	Not Covered
StReqAddrKey	436	Not Covered
StReqDataKey	446	Not Covered
StRmaRsp	520	Not Covered
StRmaWipe	434	Not Covered
StWait	457	Not Covered

transitions	Line No.	Covered	Tests
StEntropyReseed->StDisabled	572	Not Covered
StEntropyReseed->StRmaWipe	507	Not Covered
StIdle->StDisabled	572	Not Covered
StIdle->StReqAddrKey	436	Not Covered
StIdle->StRmaWipe	434	Not Covered
StInvalid->StDisabled	572	Not Covered
StReadEval->StDisabled	572	Not Covered
StReadEval->StReadSeeds	485	Not Covered
StReadSeeds->StDisabled	572	Not Covered
StReadSeeds->StReadEval	478	Not Covered
StReadSeeds->StWait	475	Not Covered
StReqAddrKey->StDisabled	572	Not Covered
StReqAddrKey->StReqDataKey	446	Not Covered
StReqAddrKey->StRmaWipe	444	Not Covered
StReqDataKey->StDisabled	572	Not Covered
StReqDataKey->StReadSeeds	457	Not Covered
StReqDataKey->StRmaWipe	454	Not Covered
StReqDataKey->StWait	457	Not Covered
StRmaRsp->StDisabled	572	Not Covered
StRmaRsp->StInvalid	534	Not Covered
StRmaWipe->StDisabled	572	Not Covered
StRmaWipe->StInvalid	520	Not Covered
StRmaWipe->StRmaRsp	520	Not Covered
StWait->StDisabled	572	Not Covered
StWait->StEntropyReseed	499	Not Covered

Summary for FSM :: rma_state_q

	Total	Covered	Percent
States	10	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: rma_state_q

---

states	Line No.	Covered	Tests
StRmaDisabled	785	Not Covered
StRmaErase	796	Not Covered
StRmaEraseWait	809	Not Covered
StRmaIdle	800	Not Covered
StRmaInvalid	872	Not Covered
StRmaPageSel	787	Not Covered
StRmaProgram	822	Not Covered
StRmaProgramWait	836	Not Covered
StRmaRdVerify	847	Not Covered
StRmaWordSel	815	Not Covered

transitions	Line No.	Covered	Tests
StRmaErase->StRmaEraseWait	809	Not Covered
StRmaEraseWait->StRmaWordSel	815	Not Covered
StRmaIdle->StRmaDisabled	785	Not Covered
StRmaIdle->StRmaPageSel	787	Not Covered
StRmaPageSel->StRmaDisabled	794	Not Covered
StRmaPageSel->StRmaErase	796	Not Covered
StRmaPageSel->StRmaIdle	800	Not Covered
StRmaProgram->StRmaProgramWait	836	Not Covered
StRmaProgramWait->StRmaRdVerify	847	Not Covered
StRmaRdVerify->StRmaWordSel	859	Not Covered
StRmaWordSel->StRmaDisabled	820	Not Covered
StRmaWordSel->StRmaPageSel	826	Not Covered
StRmaWordSel->StRmaProgram	822	Not Covered

---

Branch Coverage for Module : flash_ctrl_lcmgr

	Line No.	Total	Covered	Percent
Branches		94	0	0.00
TERNARY	892	2	0	0.00
TERNARY	893	2	0	0.00
TERNARY	896	2	0	0.00
TERNARY	897	2	0	0.00
TERNARY	898	2	0	0.00
TERNARY	900	2	0	0.00
IF	152	2	0	0.00
IF	174	2	0	0.00
IF	227	2	0	0.00
IF	251	2	0	0.00
IF	264	4	0	0.00
IF	359	5	0	0.00
CASE	427	27	0	0.00
IF	569	2	0	0.00
IF	613	2	0	0.00
IF	673	2	0	0.00
IF	688	7	0	0.00
IF	705	2	0	0.00
CASE	777	23	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_lcmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	892	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	893	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	896	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	897	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	898	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	900	(seed_phase) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	152	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	174	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	227	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	251	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	264	if ((!rst_ni))
-2-:	266	if (((seed_phase && validate_q) && rvalid_i))
-3-:	270	if ((seed_phase && rvalid_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	359	if ((!rst_ni))
-2-:	363	if ((addr_key_req_d && addr_key_ack_q))
-3-:	368	if ((data_key_req_d && data_key_ack_q))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	-	Not Covered
0	-	1	Not Covered
0	-	0	Not Covered

	LineNo.	Expression
-1-:	427	case (state_q)
-2-:	433	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqInit]))
-3-:	435	if (init_q)
-4-:	443	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey]))
-5-:	445	if (addr_key_ack_q)
-6-:	453	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqKey]))
-7-:	455	if (data_key_ack_q)
-8-:	457	(provision_en_i) ? 
-9-:	473	if ((seed_cnt_q == flash_ctrl_pkg::NumSeeds))
-10-:	476	if (done_i)
-11-:	487	if (validate_q)
-12-:	498	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_req[RmaReqWait]))
-13-:	506	if (edn_ack_i)
-14-:	516	if (((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done))
-15-:	521	if (rma_wipe_done)
-16-:	533	if (lc_ctrl_pkg::lc_tx_test_false_loose(err_sts_q))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StIdle	0	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StReqAddrKey	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StReqAddrKey	-	-	0	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StReqAddrKey	-	-	0	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StReqDataKey	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StReqDataKey	-	-	-	-	0	1	1	-	-	-	-	-	-	-	-	Not Covered
StReqDataKey	-	-	-	-	0	1	0	-	-	-	-	-	-	-	-	Not Covered
StReqDataKey	-	-	-	-	0	0	-	-	-	-	-	-	-	-	-	Not Covered
StReadSeeds	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
StReadSeeds	-	-	-	-	-	-	-	0	1	-	-	-	-	-	-	Not Covered
StReadSeeds	-	-	-	-	-	-	-	0	0	-	-	-	-	-	-	Not Covered
StReadEval	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Not Covered
StReadEval	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Not Covered
StWait	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
StWait	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
StEntropyReseed	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Not Covered
StEntropyReseed	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	Not Covered
StRmaWipe	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
StRmaWipe	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Not Covered
StRmaWipe	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	Not Covered
StRmaRsp	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StRmaRsp	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StInvalid	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	569	if (((prim_mubi_pkg::mubi4_test_true_loose(disable_i) && (state_d != StInvalid)) && (!rma_done)))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	613	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	673	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	688	if ((!rst_ni))
-2-:	690	if (beat_cnt_clr)
-3-:	692	if (prog_cnt_en)
-4-:	693	if ((wvalid_o && wready_i))
-5-:	696	if (rd_cnt_en)
-6-:	697	if ((rvalid_i && rready_o))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Not Covered
0	1	-	-	-	-	Not Covered
0	0	1	1	-	-	Not Covered
0	0	1	0	-	-	Not Covered
0	0	0	-	1	1	Not Covered
0	0	0	-	1	0	Not Covered
0	0	0	-	0	-	Not Covered

	LineNo.	Expression
-1-:	705	if (((prog_cnt_en && wvalid_o) && wready_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	777	case (rma_state_q)
-2-:	784	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-3-:	786	if (rma_wipe_req_int)
-4-:	793	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-5-:	795	if ((page_cnt < end_page))
-6-:	807	if (done_i)
-7-:	819	if (prim_mubi_pkg::mubi4_test_true_loose(disable_i))
-8-:	821	if ((word_cnt < flash_ctrl_pkg::BusWordsPerPage))
-9-:	835	if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i))
-10-:	844	if (done_i)
-11-:	856	if (((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i))
-12-:	862	if ((rvalid_i && rready_o))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	Status	Tests
StRmaIdle	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StRmaIdle	0	1	-	-	-	-	-	-	-	-	-	Not Covered
StRmaIdle	0	0	-	-	-	-	-	-	-	-	-	Not Covered
StRmaPageSel	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StRmaPageSel	-	-	0	1	-	-	-	-	-	-	-	Not Covered
StRmaPageSel	-	-	0	0	-	-	-	-	-	-	-	Not Covered
StRmaErase	-	-	-	-	1	-	-	-	-	-	-	Not Covered
StRmaErase	-	-	-	-	0	-	-	-	-	-	-	Not Covered
StRmaEraseWait	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StRmaWordSel	-	-	-	-	-	1	-	-	-	-	-	Not Covered
StRmaWordSel	-	-	-	-	-	0	1	-	-	-	-	Not Covered
StRmaWordSel	-	-	-	-	-	0	0	-	-	-	-	Not Covered
StRmaProgram	-	-	-	-	-	-	-	1	-	-	-	Not Covered
StRmaProgram	-	-	-	-	-	-	-	0	-	-	-	Not Covered
StRmaProgramWait	-	-	-	-	-	-	-	-	1	-	-	Not Covered
StRmaProgramWait	-	-	-	-	-	-	-	-	0	-	-	Not Covered
StRmaRdVerify	-	-	-	-	-	-	-	-	-	1	-	Not Covered
StRmaRdVerify	-	-	-	-	-	-	-	-	-	0	-	Not Covered
StRmaRdVerify	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StRmaRdVerify	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StRmaDisabled	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StRmaInvalid	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	Not Covered