Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync	0.00	0.00
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync	0.00	0.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync	0.00	0.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync	0.00	0.00
tb.dut.u_lc_seed_hw_rd_en_sync	0.00	0.00
tb.dut.u_flash_hw_if.u_sync_rma_req	0.00	0.00
tb.dut.u_prog_tl_gate.u_err_en_sync	0.00	0.00
tb.dut.u_lc_escalation_en_sync	0.00	0.00
tb.dut.u_tl_gate.u_err_en_sync	0.00	0.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync	0.00	0.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_flops.u_prim_flop_2sync	0.00	0.00				0.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_flops.u_prim_flop_2sync	0.00	0.00				0.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_flops.u_prim_flop_2sync	0.00	0.00				0.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_flops.u_prim_flop_2sync	0.00	0.00				0.00

---

Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_flops.u_prim_flop_2sync	0.00	0.00				0.00

---

Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_flash_hw_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[3].u_prim_buf	0.00	0.00
gen_flops.u_prim_flop_2sync	0.00	0.00				0.00

---

Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_prog_tl_gate

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[3].u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.u_lc_escalation_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_flops.u_prim_flop_2sync	0.00	0.00				0.00

---

Module Instance : tb.dut.u_tl_gate.u_err_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_tl_gate

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[3].u_prim_buf	0.00	0.00

---

Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[1].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[2].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[3].gen_bits[3].u_prim_buf	0.00	0.00
gen_buffs[4].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[4].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[4].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[4].gen_bits[3].u_prim_buf	0.00	0.00
gen_flops.u_prim_flop_2sync	0.00	0.00				0.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

SCORE	LINE
0.00	0.00

tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

SCORE	LINE
0.00	0.00

tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

SCORE	LINE
0.00	0.00

tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

SCORE	LINE
0.00	0.00

tb.dut.u_lc_seed_hw_rd_en_sync

SCORE	LINE
0.00	0.00

tb.dut.u_lc_escalation_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
ALWAYS	68	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	0	1
106	0	1

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_flash_hw_if.u_sync_rma_req

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
ALWAYS	68	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	0	1
106	0	3

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_prog_tl_gate.u_err_en_sync

SCORE	LINE
0.00	0.00

tb.dut.u_tl_gate.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	0	1
106	0	2

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_eflash.u_lc_nvm_debug_en_sync

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
ALWAYS	68	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	0	1
106	0	5

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
ALWAYS	68	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	0	1
106	0	1

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
ALWAYS	68	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	0	1
106	0	1

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
ALWAYS	68	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	0	1
106	0	1

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
ALWAYS	68	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	0	1
106	0	1

Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
ALWAYS	68	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	0	1
106	0	1

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req

	Line No.	Total	Covered	Percent
TOTAL		4	0	0.00
ALWAYS	68	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	0	1
106	0	3

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	0	1
106	0	2

Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	0	0.00
ALWAYS	68	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	0	1
106	0	1

Line Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	0	0.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	0	1
106	0	2

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
ALWAYS	68	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00
CONT_ASSIGN	106	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	0	1
106	0	5