FLASH_CTRL Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: b938dde05c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke flash_ctrl_smoke 4.614m 710.687us 50 50 100.00
V1 smoke_hw flash_ctrl_smoke_hw 26.280s 16.072us 5 5 100.00
V1 csr_hw_reset flash_ctrl_csr_hw_reset 32.090s 33.364us 5 5 100.00
V1 csr_rw flash_ctrl_csr_rw 17.610s 548.394us 20 20 100.00
V1 csr_bit_bash flash_ctrl_csr_bit_bash 1.002m 659.843us 5 5 100.00
V1 csr_aliasing flash_ctrl_csr_aliasing 1.125m 5.077ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset flash_ctrl_csr_mem_rw_with_rand_reset 20.270s 57.041us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr flash_ctrl_csr_rw 17.610s 548.394us 20 20 100.00
flash_ctrl_csr_aliasing 1.125m 5.077ms 5 5 100.00
V1 mem_walk flash_ctrl_mem_walk 13.550s 53.410us 5 5 100.00
V1 mem_partial_access flash_ctrl_mem_partial_access 13.860s 245.378us 5 5 100.00
V1 TOTAL 120 120 100.00
V2 sw_op flash_ctrl_sw_op 26.420s 36.252us 5 5 100.00
V2 host_read_direct flash_ctrl_host_dir_rd 2.001m 253.307us 5 5 100.00
V2 rma_hw_if flash_ctrl_hw_rma 33.599m 251.159ms 3 3 100.00
flash_ctrl_hw_rma_reset 16.769m 760.547ms 20 20 100.00
flash_ctrl_lcmgr_intg 13.890s 26.174us 20 20 100.00
V2 host_controller_arb flash_ctrl_host_ctrl_arb 46.271m 265.391ms 5 5 100.00
V2 erase_suspend flash_ctrl_erase_suspend 8.053m 6.153ms 5 5 100.00
V2 program_reset flash_ctrl_prog_reset 34.130s 642.818us 30 30 100.00
V2 full_memory_access flash_ctrl_full_mem_access 1.138h 543.886ms 5 5 100.00
V2 rd_buff_eviction flash_ctrl_rd_buff_evict 1.960m 738.924us 5 5 100.00
V2 rd_buff_eviction_w_ecc flash_ctrl_rw_evict 37.930s 183.871us 40 40 100.00
flash_ctrl_rw_evict_all_en 38.200s 115.517us 40 40 100.00
flash_ctrl_re_evict 40.170s 295.480us 20 20 100.00
V2 host_arb flash_ctrl_phy_arb 9.330m 4.245ms 20 20 100.00
V2 host_interleave flash_ctrl_phy_arb 9.330m 4.245ms 20 20 100.00
V2 memory_protection flash_ctrl_mp_regions 20.260m 60.671ms 19 20 95.00
V2 fetch_code flash_ctrl_fetch_code 29.780s 3.247ms 10 10 100.00
V2 all_partitions flash_ctrl_rand_ops 25.469m 1.592ms 20 20 100.00
V2 error_mp flash_ctrl_error_mp 43.070m 5.773ms 10 10 100.00
V2 error_prog_win flash_ctrl_error_prog_win 18.195m 2.992ms 10 10 100.00
V2 error_prog_type flash_ctrl_error_prog_type 45.800m 2.743ms 5 5 100.00
V2 error_read_seed flash_ctrl_hw_read_seed_err 13.720s 133.099us 20 20 100.00
V2 read_write_overflow flash_ctrl_oversize_error 3.044m 9.185ms 5 5 100.00
V2 flash_ctrl_disable flash_ctrl_disable 22.730s 30.035us 50 50 100.00
V2 flash_ctrl_connect flash_ctrl_connect 16.170s 19.913us 80 80 100.00
V2 stress_all flash_ctrl_stress_all 23.469m 668.603us 5 5 100.00
V2 secret_partition flash_ctrl_hw_sec_otp 4.250m 6.658ms 50 50 100.00
flash_ctrl_otp_reset 2.269m 80.241us 80 80 100.00
V2 isolation_partition flash_ctrl_hw_rma 33.599m 251.159ms 3 3 100.00
V2 interrupts flash_ctrl_intr_rd 3.538m 1.352ms 40 40 100.00
flash_ctrl_intr_wr 2.547m 60.187ms 10 10 100.00
flash_ctrl_intr_rd_slow_flash 4.969m 9.474ms 40 40 100.00
flash_ctrl_intr_wr_slow_flash 10.572m 651.080ms 10 10 100.00
V2 invalid_op flash_ctrl_invalid_op 1.516m 3.884ms 20 20 100.00
V2 mid_op_rst flash_ctrl_mid_op_rst 1.196m 953.298us 5 5 100.00
V2 double_bit_err flash_ctrl_read_word_sweep_derr 22.740s 62.407us 5 5 100.00
flash_ctrl_ro_derr 2.589m 1.546ms 10 10 100.00
flash_ctrl_rw_derr 11.673m 17.567ms 10 10 100.00
flash_ctrl_derr_detect 1.780m 322.082us 5 5 100.00
flash_ctrl_integrity 11.613m 19.206ms 5 5 100.00
V2 single_bit_err flash_ctrl_read_word_sweep_serr 22.950s 54.269us 5 5 100.00
flash_ctrl_ro_serr 2.355m 1.167ms 10 10 100.00
flash_ctrl_rw_serr 12.755m 4.986ms 9 10 90.00
V2 singlebit_err_counter flash_ctrl_serr_counter 1.300m 2.835ms 5 5 100.00
V2 singlebit_err_address flash_ctrl_serr_address 1.715m 5.317ms 5 5 100.00
V2 scramble flash_ctrl_wo 3.447m 4.994ms 20 20 100.00
flash_ctrl_write_word_sweep 14.190s 38.085us 1 1 100.00
flash_ctrl_read_word_sweep 14.100s 344.798us 1 1 100.00
flash_ctrl_ro 2.044m 2.126ms 20 20 100.00
flash_ctrl_rw 9.335m 12.178ms 20 20 100.00
V2 filesystem_support flash_ctrl_fs_sup 36.480s 1.150ms 5 5 100.00
V2 rma_write_process_error flash_ctrl_rma_err 17.935m 163.830ms 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 5.172m 10.012ms 20 20 100.00
V2 alert_test flash_ctrl_alert_test 14.520s 272.369us 50 50 100.00
V2 intr_test flash_ctrl_intr_test 13.930s 24.977us 50 50 100.00
V2 tl_d_oob_addr_access flash_ctrl_tl_errors 19.330s 330.729us 20 20 100.00
V2 tl_d_illegal_access flash_ctrl_tl_errors 19.330s 330.729us 20 20 100.00
V2 tl_d_outstanding_access flash_ctrl_csr_hw_reset 32.090s 33.364us 5 5 100.00
flash_ctrl_csr_rw 17.610s 548.394us 20 20 100.00
flash_ctrl_csr_aliasing 1.125m 5.077ms 5 5 100.00
flash_ctrl_same_csr_outstanding 35.760s 883.249us 20 20 100.00
V2 tl_d_partial_access flash_ctrl_csr_hw_reset 32.090s 33.364us 5 5 100.00
flash_ctrl_csr_rw 17.610s 548.394us 20 20 100.00
flash_ctrl_csr_aliasing 1.125m 5.077ms 5 5 100.00
flash_ctrl_same_csr_outstanding 35.760s 883.249us 20 20 100.00
V2 TOTAL 1011 1013 99.80
V2S shadow_reg_update_error flash_ctrl_shadow_reg_errors 16.310s 17.479us 20 20 100.00
V2S shadow_reg_read_clear_staged_value flash_ctrl_shadow_reg_errors 16.310s 17.479us 20 20 100.00
V2S shadow_reg_storage_error flash_ctrl_shadow_reg_errors 16.310s 17.479us 20 20 100.00
V2S shadowed_reset_glitch flash_ctrl_shadow_reg_errors 16.310s 17.479us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw flash_ctrl_shadow_reg_errors_with_csr_rw 16.030s 60.770us 20 20 100.00
V2S tl_intg_err flash_ctrl_sec_cm 1.322h 19.645ms 5 5 100.00
flash_ctrl_tl_intg_err 15.434m 1.459ms 20 20 100.00
V2S sec_cm_reg_bus_integrity flash_ctrl_tl_intg_err 15.434m 1.459ms 20 20 100.00
V2S sec_cm_host_bus_integrity flash_ctrl_tl_intg_err 15.434m 1.459ms 20 20 100.00
V2S sec_cm_mem_bus_integrity flash_ctrl_rd_intg 32.160s 233.693us 3 3 100.00
flash_ctrl_wr_intg 14.630s 52.544us 3 3 100.00
V2S sec_cm_scramble_key_sideload flash_ctrl_smoke 4.614m 710.687us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi flash_ctrl_otp_reset 2.269m 80.241us 80 80 100.00
flash_ctrl_disable 22.730s 30.035us 50 50 100.00
flash_ctrl_sec_info_access 1.470m 25.535ms 50 50 100.00
flash_ctrl_connect 16.170s 19.913us 80 80 100.00
V2S sec_cm_ctrl_config_regwen flash_ctrl_config_regwen 13.840s 29.865us 5 5 100.00
V2S sec_cm_data_regions_config_regwen flash_ctrl_csr_rw 17.610s 548.394us 20 20 100.00
V2S sec_cm_data_regions_config_shadow flash_ctrl_shadow_reg_errors 16.310s 17.479us 20 20 100.00
V2S sec_cm_info_regions_config_regwen flash_ctrl_csr_rw 17.610s 548.394us 20 20 100.00
V2S sec_cm_info_regions_config_shadow flash_ctrl_shadow_reg_errors 16.310s 17.479us 20 20 100.00
V2S sec_cm_bank_config_regwen flash_ctrl_csr_rw 17.610s 548.394us 20 20 100.00
V2S sec_cm_bank_config_shadow flash_ctrl_shadow_reg_errors 16.310s 17.479us 20 20 100.00
V2S sec_cm_mem_ctrl_global_esc flash_ctrl_disable 22.730s 30.035us 50 50 100.00
V2S sec_cm_mem_ctrl_local_esc flash_ctrl_rd_intg 32.160s 233.693us 3 3 100.00
flash_ctrl_access_after_disable 13.650s 17.658us 3 3 100.00
V2S sec_cm_mem_disable_config_mubi flash_ctrl_disable 22.730s 30.035us 50 50 100.00
V2S sec_cm_exec_config_redun flash_ctrl_fetch_code 29.780s 3.247ms 10 10 100.00
V2S sec_cm_mem_scramble flash_ctrl_rw 9.335m 12.178ms 20 20 100.00
V2S sec_cm_mem_integrity flash_ctrl_rw_serr 12.755m 4.986ms 9 10 90.00
flash_ctrl_rw_derr 11.673m 17.567ms 10 10 100.00
flash_ctrl_integrity 11.613m 19.206ms 5 5 100.00
V2S sec_cm_rma_entry_mem_sec_wipe flash_ctrl_hw_rma 33.599m 251.159ms 3 3 100.00
V2S sec_cm_ctrl_fsm_sparse flash_ctrl_sec_cm 1.322h 19.645ms 5 5 100.00
V2S sec_cm_phy_fsm_sparse flash_ctrl_sec_cm 1.322h 19.645ms 5 5 100.00
V2S sec_cm_phy_prog_fsm_sparse flash_ctrl_sec_cm 1.322h 19.645ms 5 5 100.00
V2S sec_cm_ctr_redun flash_ctrl_sec_cm 1.322h 19.645ms 5 5 100.00
V2S sec_cm_phy_arbiter_ctrl_redun flash_ctrl_phy_arb_redun 26.010s 806.186us 5 5 100.00
V2S sec_cm_phy_host_grant_ctrl_consistency flash_ctrl_phy_host_grant_err 14.100s 14.912us 5 5 100.00
V2S sec_cm_phy_ack_ctrl_consistency flash_ctrl_phy_ack_consistency 14.100s 15.264us 5 5 100.00
V2S sec_cm_fifo_ctr_redun flash_ctrl_sec_cm 1.322h 19.645ms 5 5 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 1.322h 19.645ms 5 5 100.00
V2S sec_cm_prog_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 1.322h 19.645ms 5 5 100.00
V2S TOTAL 144 144 100.00
V3 asymmetric_read_path flash_ctrl_rd_ooo 48.030s 101.718us 1 1 100.00
V3 stress_all_with_rand_reset flash_ctrl_stress_all_with_rand_reset 0 0 --
V3 TOTAL 1 1 100.00
TOTAL 1276 1278 99.84

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 55 55 53 96.36
V2S 12 12 12 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.40 95.78 94.15 98.85 91.84 98.05 98.00 98.12

Failure Buckets

Past Results