GPIO Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.470s	81.729us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.400s	80.259us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	208.460us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	43.556us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.080s	259.462us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.880s	137.844us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.370s	52.280us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	43.556us	20	20	100.00
		gpio_csr_aliasing	0.880s	137.844us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.240s	71.335us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.280s	68.719us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.900s	154.711us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.520s	103.493us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.680s	466.840us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.640s	820.647us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.150s	3.570ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.290s	2.278ms	50	50	100.00
V2	full_random	gpio_full_random	1.030s	333.817us	50	50	100.00
V2	stress_all	gpio_stress_all	3.066m	53.053ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.620s	16.806us	50	50	100.00
V2	intr_test	gpio_intr_test	0.650s	22.931us	17	50	34.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.060s	139.530us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.060s	139.530us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	43.556us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	113.898us	20	20	100.00
		gpio_csr_aliasing	0.880s	137.844us	5	5	100.00
		gpio_csr_hw_reset	0.660s	208.460us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	43.556us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	113.898us	20	20	100.00
		gpio_csr_aliasing	0.880s	137.844us	5	5	100.00
		gpio_csr_hw_reset	0.660s	208.460us	5	5	100.00
V2		TOTAL			607	640	94.84
V2S	tl_intg_err	gpio_tl_intg_err	1.430s	260.879us	20	20	100.00
		gpio_sec_cm	0.970s	132.201us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.430s	260.879us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	40.887m	104.343ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			837	870	96.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	14	14	13	92.86
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.07	99.10	100.00	--	99.80	99.68	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:455) [gpio_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRgpio_reg_block.intr_state

has 33 failures:

Test gpio_intr_test has 33 failures.

0.gpio_intr_test.3373177196
Line 219, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_intr_test/latest/run.log

  UVM_ERROR @  15249266 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3240321367 [0xc1236157]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @  15249266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.gpio_intr_test.341839796
Line 223, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_intr_test/latest/run.log

  UVM_ERROR @   3549436 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 1977547257 [0x75def9f9]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   3549436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 31 more failures.