GPIO Simulation Results

Wednesday January 03 2024 20:02:50 UTC

GitHub Revision: 748235cbb6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25438953283828179064589190240910206115356752103516363191807863392753441298838

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.500s 385.070us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.410s 193.370us 50 50 100.00
gpio_smoke_en_cdc_prim 1.440s 348.951us 46 50 92.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.410s 98.069us 42 50 84.00
V1 csr_hw_reset gpio_csr_hw_reset 0.650s 21.412us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.620s 11.850us 19 20 95.00
V1 csr_bit_bash gpio_csr_bit_bash 2.830s 82.220us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.840s 64.963us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.100s 77.157us 19 20 95.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.620s 11.850us 19 20 95.00
gpio_csr_aliasing 0.840s 64.963us 5 5 100.00
V1 TOTAL 241 255 94.51
V2 direct_and_masked_out gpio_random_dout_din 1.220s 130.980us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.240s 131.815us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.950s 53.096us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.510s 114.250us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.710s 481.358us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.890s 92.360us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 27.140s 780.268us 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.620s 1.592ms 50 50 100.00
V2 full_random gpio_full_random 1.090s 75.291us 50 50 100.00
V2 stress_all gpio_stress_all 3.927m 45.253ms 50 50 100.00
V2 alert_test gpio_alert_test 0.610s 13.569us 50 50 100.00
V2 intr_test gpio_intr_test 0.670s 15.101us 46 50 92.00
V2 tl_d_oob_addr_access gpio_tl_errors 2.910s 189.482us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 2.910s 189.482us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.620s 11.850us 19 20 95.00
gpio_same_csr_outstanding 0.820s 25.896us 19 20 95.00
gpio_csr_aliasing 0.840s 64.963us 5 5 100.00
gpio_csr_hw_reset 0.650s 21.412us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.620s 11.850us 19 20 95.00
gpio_same_csr_outstanding 0.820s 25.896us 19 20 95.00
gpio_csr_aliasing 0.840s 64.963us 5 5 100.00
gpio_csr_hw_reset 0.650s 21.412us 5 5 100.00
V2 TOTAL 635 640 99.22
V2S tl_intg_err gpio_tl_intg_err 1.440s 600.540us 19 20 95.00
gpio_sec_cm 0.950s 86.498us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.440s 600.540us 19 20 95.00
V2S TOTAL 24 25 96.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 34.594m 109.867ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 950 970 97.94

Testplan Progress

Items Total Written Passing Progress
V1 9 9 5 55.56
V2 14 14 12 85.71
V2S 2 2 1 50.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.61 99.06 99.10 100.00 -- 99.80 99.68 100.00

Failure Buckets

Past Results