GPIO Simulation Results

Sunday January 14 2024 20:02:50 UTC

GitHub Revision: 5f48fbc0e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 17974844803940076144755676589184454804069451770040436570888369542024131598097

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.480s 320.463us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.520s 207.695us 50 50 100.00
gpio_smoke_en_cdc_prim 1.470s 51.461us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.500s 53.663us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.630s 14.689us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.650s 109.737us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.270s 1.262ms 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.830s 30.327us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.380s 27.786us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.650s 109.737us 20 20 100.00
gpio_csr_aliasing 0.830s 30.327us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.310s 38.829us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.330s 217.824us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.960s 52.011us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.490s 118.100us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.470s 2.557ms 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.630s 176.312us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 26.660s 3.009ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.360s 555.767us 50 50 100.00
V2 full_random gpio_full_random 1.130s 371.521us 50 50 100.00
V2 stress_all gpio_stress_all 3.642m 30.640ms 50 50 100.00
V2 alert_test gpio_alert_test 0.620s 15.049us 50 50 100.00
V2 intr_test gpio_intr_test 0.670s 49.631us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.110s 188.911us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.110s 188.911us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.650s 109.737us 20 20 100.00
gpio_same_csr_outstanding 0.880s 33.320us 20 20 100.00
gpio_csr_aliasing 0.830s 30.327us 5 5 100.00
gpio_csr_hw_reset 0.630s 14.689us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.650s 109.737us 20 20 100.00
gpio_same_csr_outstanding 0.880s 33.320us 20 20 100.00
gpio_csr_aliasing 0.830s 30.327us 5 5 100.00
gpio_csr_hw_reset 0.630s 14.689us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.530s 232.918us 20 20 100.00
gpio_sec_cm 0.930s 193.577us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.530s 232.918us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 43.247m 117.821ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 970 970 100.00

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.61 99.06 99.10 100.00 -- 99.80 99.68 100.00

Past Results