GPIO Simulation Results

Wednesday February 28 2024 23:53:28 UTC

GitHub Revision: 32ed2c4230

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 10708067410766204292161266966839433462058030635847883045650346145926493105783

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.820s	83.167us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.550s	136.099us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.470s	287.294us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.580s	58.430us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.620s	55.991us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.690s	14.906us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.490s	1.287ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.840s	31.463us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.600s	64.662us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.690s	14.906us	20	20	100.00
		gpio_csr_aliasing	0.840s	31.463us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.500s	56.122us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.450s	71.535us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.970s	136.498us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.680s	109.597us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	4.020s	127.425us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.310s	217.479us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.340s	499.553us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	7.310s	486.848us	50	50	100.00
V2	full_random	gpio_full_random	1.240s	200.028us	50	50	100.00
V2	stress_all	gpio_stress_all	4.573m	21.305ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	61.500us	50	50	100.00
V2	intr_test	gpio_intr_test	0.670s	13.586us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.530s	324.550us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.530s	324.550us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.690s	14.906us	20	20	100.00
		gpio_same_csr_outstanding	1.000s	122.163us	20	20	100.00
		gpio_csr_aliasing	0.840s	31.463us	5	5	100.00
		gpio_csr_hw_reset	0.620s	55.991us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.690s	14.906us	20	20	100.00
		gpio_same_csr_outstanding	1.000s	122.163us	20	20	100.00
		gpio_csr_aliasing	0.840s	31.463us	5	5	100.00
		gpio_csr_hw_reset	0.620s	55.991us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.790s	493.828us	20	20	100.00
		gpio_sec_cm	0.990s	377.239us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.790s	493.828us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	52.818m	799.119ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			940	970	96.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:788) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
  • Test gpio_stress_all_with_rand_reset has 30 failures.

    • 0.gpio_stress_all_with_rand_reset.82329857988685987228421406100318878921635724570531862794519998051835351202670
      Line 6957, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 82671285834 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 82671285834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.9587212939235648994360388331692247575867496701319792475929553695657604084127
      Line 5067, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 45753100429 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 45753100429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 28 more failures.

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