GPIO Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: e0c4026501

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.530s	110.453us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.480s	85.278us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.510s	104.196us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.480s	89.347us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	58.591us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.680s	15.128us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.710s	375.993us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.850s	213.045us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.810s	71.600us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.680s	15.128us	20	20	100.00
		gpio_csr_aliasing	0.850s	213.045us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.430s	297.407us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.320s	56.957us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.000s	51.111us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.530s	445.311us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.630s	250.043us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.810s	184.680us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	26.820s	1.040ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.780s	394.136us	50	50	100.00
V2	full_random	gpio_full_random	1.150s	155.941us	50	50	100.00
V2	stress_all	gpio_stress_all	3.391m	18.788ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.660s	47.890us	50	50	100.00
V2	intr_test	gpio_intr_test	0.650s	40.911us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.460s	469.517us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.460s	469.517us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.680s	15.128us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	138.643us	20	20	100.00
		gpio_csr_aliasing	0.850s	213.045us	5	5	100.00
		gpio_csr_hw_reset	0.660s	58.591us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.680s	15.128us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	138.643us	20	20	100.00
		gpio_csr_aliasing	0.850s	213.045us	5	5	100.00
		gpio_csr_hw_reset	0.660s	58.591us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.460s	909.925us	20	20	100.00
		gpio_sec_cm	0.930s	93.678us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.460s	909.925us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	48.768m	146.681ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			945	970	97.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:788) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
  • Test gpio_stress_all_with_rand_reset has 25 failures.

    • 0.gpio_stress_all_with_rand_reset.3379350816299494775442131859543967354870813179718277678299147355819013611409
      Line 17677, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 448550452510 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 448550452510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.74151628704454269108839084321331426640468644752419593681442026351343101410447
      Line 11599, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 64218305577 ps: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 64218305577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

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