GPIO Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: 0cdf265eaa

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.550s	111.420us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.420s	153.158us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.690s	307.012us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.590s	57.420us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.650s	16.921us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.680s	20.123us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.920s	853.603us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.910s	144.604us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.520s	71.719us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.680s	20.123us	20	20	100.00
		gpio_csr_aliasing	0.910s	144.604us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.410s	75.153us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.370s	61.809us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.010s	177.558us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.440s	109.830us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.600s	677.578us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.690s	448.236us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	27.950s	3.886ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.690s	1.510ms	50	50	100.00
V2	full_random	gpio_full_random	1.120s	203.687us	50	50	100.00
V2	stress_all	gpio_stress_all	4.107m	21.579ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	13.017us	50	50	100.00
V2	intr_test	gpio_intr_test	0.660s	12.286us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.880s	59.538us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.880s	59.538us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.680s	20.123us	20	20	100.00
		gpio_same_csr_outstanding	0.940s	40.510us	20	20	100.00
		gpio_csr_aliasing	0.910s	144.604us	5	5	100.00
		gpio_csr_hw_reset	0.650s	16.921us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.680s	20.123us	20	20	100.00
		gpio_same_csr_outstanding	0.940s	40.510us	20	20	100.00
		gpio_csr_aliasing	0.910s	144.604us	5	5	100.00
		gpio_csr_hw_reset	0.650s	16.921us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.860s	1.511ms	20	20	100.00
		gpio_sec_cm	0.910s	214.638us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.860s	1.511ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	47.639m	409.987ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			941	970	97.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:815) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
  • Test gpio_stress_all_with_rand_reset has 29 failures.

    • 0.gpio_stress_all_with_rand_reset.6729509401770997132259550462243123445493755018812533271439329880224687115433
      Line 351, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 304808834 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 304808834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.56738381786282967287047981806466745777559333197201603083631125241712705460439
      Line 4432, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 214978308074 ps: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 214978308074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

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