GPIO Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.400s	146.741us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.390s	80.817us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.520s	94.038us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.570s	79.477us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.710s	44.956us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.720s	29.490us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.110s	1.043ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.830s	31.118us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.650s	38.978us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.720s	29.490us	20	20	100.00
		gpio_csr_aliasing	0.830s	31.118us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.360s	64.494us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.320s	290.578us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.920s	31.371us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.410s	418.007us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.600s	126.066us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.650s	375.488us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.920s	1.026ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.470s	2.550ms	50	50	100.00
V2	full_random	gpio_full_random	1.070s	315.809us	50	50	100.00
V2	stress_all	gpio_stress_all	4.098m	82.166ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.620s	35.396us	50	50	100.00
V2	intr_test	gpio_intr_test	0.690s	13.319us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.190s	941.987us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.190s	941.987us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.720s	29.490us	20	20	100.00
		gpio_same_csr_outstanding	0.990s	42.825us	20	20	100.00
		gpio_csr_aliasing	0.830s	31.118us	5	5	100.00
		gpio_csr_hw_reset	0.710s	44.956us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.720s	29.490us	20	20	100.00
		gpio_same_csr_outstanding	0.990s	42.825us	20	20	100.00
		gpio_csr_aliasing	0.830s	31.118us	5	5	100.00
		gpio_csr_hw_reset	0.710s	44.956us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.570s	125.322us	20	20	100.00
		gpio_sec_cm	0.980s	2.288ms	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.570s	125.322us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	38.983m	289.652ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			944	970	97.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
  • Test gpio_stress_all_with_rand_reset has 26 failures.

    • 0.gpio_stress_all_with_rand_reset.43517368586090383761077065794590310410781835837198829118582659287039936587920
      Line 10219, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 96351029375 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 96351029375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.57714173466461119957101584621614406093860114131408588023865847739061069073993
      Line 5342, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 121043514860 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 121043514860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 24 more failures.

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