GPIO Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.470s 378.015us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.590s 300.705us 50 50 100.00
gpio_smoke_en_cdc_prim 1.480s 572.501us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.560s 89.579us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.680s 39.805us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.690s 41.083us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.510s 370.491us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.830s 60.797us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.570s 63.445us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.690s 41.083us 20 20 100.00
gpio_csr_aliasing 0.830s 60.797us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.440s 75.575us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.430s 267.437us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.970s 193.006us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.380s 179.534us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.750s 686.352us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.750s 643.677us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 26.790s 3.435ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.350s 618.040us 50 50 100.00
V2 full_random gpio_full_random 1.070s 1.157ms 50 50 100.00
V2 stress_all gpio_stress_all 3.959m 41.483ms 50 50 100.00
V2 alert_test gpio_alert_test 0.650s 81.692us 50 50 100.00
V2 intr_test gpio_intr_test 0.650s 18.489us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 2.820s 248.640us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 2.820s 248.640us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.690s 41.083us 20 20 100.00
gpio_same_csr_outstanding 0.930s 552.374us 20 20 100.00
gpio_csr_aliasing 0.830s 60.797us 5 5 100.00
gpio_csr_hw_reset 0.680s 39.805us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.690s 41.083us 20 20 100.00
gpio_same_csr_outstanding 0.930s 552.374us 20 20 100.00
gpio_csr_aliasing 0.830s 60.797us 5 5 100.00
gpio_csr_hw_reset 0.680s 39.805us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.450s 114.525us 20 20 100.00
gpio_sec_cm 0.990s 316.414us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.450s 114.525us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 32.898m 120.003ms 22 50 44.00
V3 TOTAL 22 50 44.00
TOTAL 942 970 97.11

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 99.99

Failure Buckets

Past Results