GPIO Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.490s	344.173us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.530s	84.328us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.900s	1.416ms	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.590s	984.376us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.750s	34.032us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.740s	18.140us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.920s	296.386us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.720s	18.451us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.820s	136.912us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.740s	18.140us	20	20	100.00
		gpio_csr_aliasing	0.720s	18.451us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.440s	62.637us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.370s	87.694us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.020s	51.965us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.550s	113.897us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.630s	301.698us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.030s	96.873us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	29.350s	1.235ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	7.400s	1.271ms	50	50	100.00
V2	full_random	gpio_full_random	1.110s	282.910us	50	50	100.00
V2	stress_all	gpio_stress_all	4.005m	105.792ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.680s	13.522us	50	50	100.00
V2	intr_test	gpio_intr_test	0.700s	15.462us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.740s	1.094ms	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.740s	1.094ms	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.740s	18.140us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	19.940us	20	20	100.00
		gpio_csr_aliasing	0.720s	18.451us	5	5	100.00
		gpio_csr_hw_reset	0.750s	34.032us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.740s	18.140us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	19.940us	20	20	100.00
		gpio_csr_aliasing	0.720s	18.451us	5	5	100.00
		gpio_csr_hw_reset	0.750s	34.032us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.550s	280.149us	20	20	100.00
		gpio_sec_cm	1.090s	249.871us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.550s	280.149us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	48.066m	503.680ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			938	970	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
  • Test gpio_stress_all_with_rand_reset has 32 failures.

    • 0.gpio_stress_all_with_rand_reset.7233214156180605276352833300642051341644868609034307444349019856393022395246
      Line 1215, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5560204677 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5560204677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.105246652472804041648435846717798723137751210458258478404284027997265278553233
      Line 7906, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 73113732507 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 73113732507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 30 more failures.

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